Design and implementation of general AD IP core based on NiosII processor

With the rapid development of electronic technology, the demand for embedded systems is increasing and the application fields are becoming more and more extensive. Data acquisition is an indispensable part of embedded systems, and its performance directly determines whether the entire system can meet the design requirements to a certain extent. At present, the implementation of the data acquisition part basically uses AD peripherals integrated in the microcontroller or ARM chip. The performance parameters of this AD peripheral are often solidified on the chip (that is, they are unchangeable), and are inseparably combined with other on-chip peripherals, which makes the design of the entire system very limited. In addition, the styles and models of microcontrollers and ARMs on the market are very limited, and users have to make a compromise between performance and cost to meet the requirements of the designed system. Since this design scheme is unchangeable, has a small application range and poor portability, it often cannot meet customers' higher requirements.

Nios II is a second-generation RISC processor soft core developed by Altera that can be used for SOPC design. It has the characteristics of customized instructions, hardware acceleration, reconfiguration, low cost and unparalleled flexibility [1]. The general AD IP core based on the Nios II processor is a new design idea and implementation solution. It can make any AD chip on the market into an IP core and integrate it into the Nios II system. It has the characteristics of high performance, configurable parameters, portability, and scalability. It is also very flexible and practical, so it can better meet the design requirements.

This paper proposes a new solution for implementing an embedded data acquisition system based on a general AD IP core of the NiosII processor. The hardware verification is completed on the Altera FPGA chip CycloneII EP2C35F484C8 and finally applied to the design of a data acquisition system.

1 Overall Architecture of Universal AD IP Core

The universal AD IP core is designed for all AD chips. It can integrate any AD chip on the market into the NiosII system. Its overall architecture is shown in Figure 1.

The entire general AD IP core is mainly composed of four sub-modules: AD controller module, FIR filter module, FIFO buffer module and register file module with Avalon-MM Slave interface. First, the AD controller controls the AD chip to collect external analog signals. The collected data is sent to the FIR filter for digital filtering. Then, the data after digital signal processing is stored in the FIFO buffer. When the FIFO buffer data is full, an interrupt will be generated to the NIOSII processor. The top-level application can read the data in the FIFO into the memory for processing through the interrupt service program. The register file module with Avalon-MM Slave interface provides a way for the task logic of the designed AD IP core to exchange information with the Avalon switch structure. With the register file module, the NiosII processor can access the registers inside the AD IP core through the Avalon interface using the "base address + address offset" method [2].

2 Design and implementation of each module of AD IP core

Since there are so many types and models of AD chips on the market, it is impossible to explain them one by one here. This design takes a commonly used typical AD chip TLC549 as an example to explain in detail the design and implementation of each module of the IP core for this AD chip.

2.1 Design of AD controller module

This system uses the AD conversion chip TLC549, which is a low-cost, high-performance 8-bit A/D converter produced by TI. It can be easily connected to various microprocessors using a three-wire serial interface to form various low-cost measurement and control application systems [3].

This paper uses the finite state machine method to design a TLC549 controller using Verilog HDL hardware description language, thereby completing the timing control of the TLC549 AD chip. Its state transition diagram is shown in Figure 2.

As can be seen from Figure 2, the state machine is in the idle state at the beginning. At the rising edge of the next clk clock cycle, it enters the cs_low state, and in the cs_low state, the cs output pin is pulled low and delayed for 2 μs. When the 2 μs delay is completed, the state machine enters the sclk_low state, and in the sclk_low state, the sclk output pin is pulled low and delayed for 0.5 μs. When the 0.5 μs delay is completed, the state machine enters the sclk_high state, and in the sclk_high state, the sclk output pin is pulled high and delayed for 0.5 μs, and at the same time, the AD sampling value on the serial data line miso is read and stored in the shift register. When the 0.5 μs delay is completed, it enters the finish state, in which the state machine judges the number of serial data bits that have been received. If it is less than 8, it means that the serial data has not been received, and 1 is added and it enters the sclk_low state; if it is equal to 8, it means that the 8-bit AD sampling value has been received, and it enters the delay state. In the delay state, it will delay for 30 μs, and when the 30 μs delay is completed, it will enter the load state. In the load state, the state machine pulls up one clk clock cycle on the data_ready output pin and outputs the received 8-bit sampled data on the data[7..0] pin. At the next clk clock cycle rising edge, the state machine will automatically enter the idle state to perform the next AD data acquisition. This cycle repeats continuously to complete the real-time acquisition of external analog signals through the TLC549 AD chip. [page]

This paper uses the Signal Tap II embedded logic analyzer software integrated in Quartus software to perform hardware simulation on the TLC549 controller module. The waveform is shown in Figure 3.

As can be seen from Figure 3, with the timing coordination of the cs, sclk and miso signals, the data signal line outputs stable 8-bit AD sampling data, which is consistent with the external input analog value after digital-to-analog conversion, thus completing the verification of the TLC549 controller module.

The AD controller module is designed for a specific AD chip. If a different type of AD chip is selected, it is necessary to refer to the chip manual of the chip to design the AD controller module for the AD chip.

2.2 Design of FIR filter module

In practical data acquisition systems, it is often necessary to filter external analog input signals to extract useful information from the signals. In this design, this part of the function is completed by the FIR filter module. The FIR filter module is implemented using the FIR IP core provided by Altera. It is simulated by the DSP Builder tool in the Simulink software and can eventually generate the underlying HDL code. Since the highest sampling frequency of TLC549 is 40 kHz, this paper designs a low-pass filter with a sampling frequency of 40 kHz and a 3 dB cutoff frequency of 100 Hz. The simulation model of the FIR IP core established in the Simulink software is shown in Figure 4.

In Figure 4, the nco_v8_0 module and the nco_v8_1 module are two numerically controlled oscillators, which are used to generate 100 Hz and 1 kHz sinusoidal signals respectively. The signal add module is a parallel adder, which superimposes the two sinusoidal signals and outputs the sum signal. The fir_compiler_v8_0 module is a FIR IP core, which takes the sum signal output by the signal add module as input and outputs the result of digital filtering to the oscilloscope for display. The simulation results are shown in Figures 5 and 6.

As can be seen from Figure 5: the first channel is a sine signal with a frequency of 100 Hz, the second channel is a sine signal with a frequency of 1 kHz, and the third channel is the superposition of the first two channels. Figure 6 shows the waveform after digital filtering. It can be seen that only the 100 Hz frequency component exists and the 1 kHz signal is filtered out, thus completing the functional verification of the FIR IP core. The Signal Compiler tool in Figure 4 can be used to generate the underlying HDL code of the FIR IP core. [page]

The FIR filter module is implemented using the FIR IP core provided by Altera, which has the characteristics of high performance, configurability, and reusability. Designers only need to determine the type and coefficient of the filter based on the requirements of the entire system and the sampling rate of the selected AD chip, and parameterize and instantiate the IP core to complete the design of the FIR filter module for the AD chip. Therefore, this part of the design is relatively independent for different AD chips and has good versatility.

2.3 Design of FIFO Buffer Module

In order to continuously and correctly collect data and achieve seamless buffering, this design uses FIFO as data cache. Since TLC549 is an 8-bit AD chip, this design uses a 512×8 bit FIFO to store the sampled data. When the data in the FIFO is full, it will generate an interrupt signal to the Nios II CPU. The top-level application can read the data in the FIFO into the memory for processing through the interrupt service program. This will not cause data loss, and at the same time ensure the high efficiency of the CPU, which well solves the above-mentioned speed mismatch problem.

The design of the FIFO cache module is relatively independent for different AD chips. The designer only needs to determine the bit width and depth of the FIFO cache based on the accuracy, sampling rate, clock rate and other parameters of the selected AD chip, and parameterize and instantiate the FIFO to complete the design of the FIFO cache module for the AD chip. Therefore, it has good versatility.

2.4 Design of Register File Module with Avalon-MM Slave Interface

The register file module with Avalon-MM Slave interface [4] designed in this paper is a peripheral with Avalon-MM Slave port. It has two 8-bit registers, and the specific structure and function are shown in Table 1. The NiosII processor can access these two registers through the Avalon interface in the form of "base address + address offset", thereby realizing the control of the AD IP core and the reading of AD sampling data.

For some more complex AD chips (such as AD73360), it is often necessary to write control words and read status words, which requires increasing the number of registers in the register file module to complete the corresponding logical functions. The Avalon interface uses the "base address + address offset" method to access registers, which can be achieved simply by increasing the number of bits of the address line and decoding it. Therefore, it has good scalability and applicability for various complex AD chips.

3 Hardware test of the entire IP core in the NiosII system

This design uses Verilog HDL language to create a top-level file tlc549_adc_ip.v. By instantiating and interconnecting the AD controller module, FIR filter module, FIFO buffer module and register file module with Avalon-MM Slave interface, the design of the entire IP core is finally completed. Its module diagram is shown in Figure 7.

This article uses C++ language to make a top-level application test program based on NiosII processor, and uses the point drawing method to draw the continuously collected AD data into a waveform display, thereby completing the hardware function test of the entire IP core. During the test, a mixed signal composed of a 1 kHz sine signal and a 100 Hz sine signal is input to the analog input end of the AD chip, and the operation results of the entire system are displayed in the Console console of the NiosII IDE software, as shown in Figure 8.

By analyzing and calculating the sine waveform and the sampled data in Figure 8, we can see that the collected signal frequency is 100 Hz, and the signal amplitude is completely consistent with the external analog input signal, thus verifying the functional correctness of the entire IP core. The entire IP core uses 5,275 LEs, accounting for 15.8% of the total, and 4,096 storage units, accounting for 0.8% of the total. The main frequency of the system can reach 199.64 MHz. [page]

In order to verify the versatility and applicability of the AD IP core, this paper also fabricated and tested IP cores for two other AD chips (AD7476 and AD73360), and the test signals were exactly the same as those of the TLC549 IP core.

The AD7476 IP core adopts the design method of the above-mentioned general AD IP core. Its AD controller module is designed for the AD7476 12-bit serial AD chip. The parameters of the FIR filter module are the same as those of the FIR filter in the TLC549 IP core, except that the bit width of the input data is set to 12 bits. Since the sampling rate of the AD7476 chip is relatively fast, the depth of the FIFO buffer module is set to 1 024 and the bit width is set to 12 bits, which can make the NiosII CPU more efficient.

The AD73360 IP core also uses the design method of the general AD IP core mentioned above. Its AD controller module is designed for the 6-channel 16-bit serial AD chip AD73360. The parameters of its FIR filter module and FIFO buffer module are the same as the corresponding parameter settings in TLC549, except that the bit width is set to 16 bits. Since the internal registers of the AD73360 chip need to be read and written during the control process, two registers (1 read status word register and 1 write control word register) are added to the register file module to complete the reading and writing of the internal control and status registers of the AD73360 chip.

The comparison between these two AD IP cores and the TLC549 IP core is shown in Table 2. As can be seen from Table 2, the general AD IP core based on the NiosII processor proposed in this paper is applicable to AD chips with different precision, different sampling rates, different clock rates, and different numbers of channels, and has high performance and flexibility. In practical applications, if there are certain restrictions on the number of resources occupied by the IP core, the FIR filter module can be written by itself, which can greatly reduce the number of resources occupied by the IP core, thereby achieving a balance between the performance and resources of the entire IP core.

References

[1] Altera Corp. Nios II Processor Reference Manual, 2008.

[2] Li Lanying. NiosⅡ embedded soft-core SOPC design principles and applications. Beijing: Beijing University of Aeronautics and Astronautics Press, 2006.

[3] TI Inc. TLC549 datasheet.1996.

[4] Altera Corp. AVALON Bus Interface Specification Manual, 2008.