FPGA Implementation of Adaptive Filter Based on Subband Decomposition

0 Introduction

Adaptive filters have been widely used in various fields such as channel equalization, echo cancellation, system identification, spectrum estimation, etc. Adaptive filtering based on subband decomposition improves convergence performance while saving a certain amount of calculation. Adaptive filtering based on subband decomposition is to first decompose the input signal and the reference signal through the decomposition filter group, extract, subband adaptive filtering, interpolate, and obtain the output signal through the synthesis filter group. Advantages of adaptive filters based on subband decomposition:

(1) Due to the extraction of the signal, the amount of calculation required to complete the adaptive filtering is reduced;

(2) Adaptive filtering in sub-bands improves convergence performance.

1 Adaptive filter structure based on subband decomposition

The time domain structure of the adaptive filtering based on subband decomposition is shown in Figure 1. The input signal x(n) and the reference signal d(n) are decomposed and extracted in subbands, and adaptive filtering is performed on the subbands. Then, the estimated signals y0(n) and y1(n) on the subbands are interpolated and synthesized by the filter group to obtain the final synthetic signal. Among them, the filters W00(n) and W11(n) are adaptive filters on two subbands, while W01(n) and W10(n) represent inter-subband adaptive filters. This is because the filter groups are all FIR filters, which cannot have the ideal characteristics of sharp cutoff, and can only exchange approximate characteristics at the cost of length; at this time, the subband signals obtained under strict sampling must have aliasing, and inter-subband filtering needs to be added to eliminate its influence. The subband adaptive filter here adopts an adaptive filter based on the NLMS algorithm. Compared with the NLMS algorithm and the LMS algorithm. Although the amount of calculation is slightly increased, the convergence speed of the adaptive filter can be greatly improved.

2 Design of Dual-Channel Filter Bank

The relationship between the analysis and synthesis filters used in this paper is as follows:

H1(z)=H0(-z), G1(z)=-2H0(-z), G0(z)=2H1(-z). From the above expressions, we can see that the key to design is to design H0(z). As long as H0(z) is determined, H1(z), G0(z), and G1(z) can also be determined. This paper adopts the equiripple approximation design method to design the filter. The filter designed by this method exhibits equiripple frequency response characteristics. The filter designed by the equiripple approximation design method has the following advantages:

(1) Since the error is evenly distributed over the entire frequency band, the best filtering characteristics can be obtained for a fixed order N;

(2) The passband is the flattest and the stopband has the minimum attenuation and the maximum attenuation.

Matlab integrates a powerful filter design tool FDATOOL, which can complete the design, analysis and performance evaluation of various filters. The frequency characteristic curves of the four FIR filters used in the FPGA hardware implementation part of this article are shown in Figure 2.

[page]

3 System Modeling and Simulation

DSP Builder is a system-level tool for DSP development launched by Altera. It is a Simulink toolbox (ToolBox) of Matlab. As a toolbox in Simulink, DSP Builder enables FPGA to be used to design DSP system through Simulink graphical interface. It only needs to call the modules in DSP Builder toolbox.

The block diagram of the adaptive filter module based on subband decomposition in Figure 3 is composed of analysis filter subsystems h00, h01, h10, h11, synthesis filter subsystems g00, g01, extraction, interpolation, addition, subtraction, adaptive filter and other modules. h00 and h10 are completely identical low-pass filters, and h01 and h11 are completely identical high-pass filters. The amplitude-frequency characteristic curves of h00, h01, g00, g01 are shown in Figure 2. h00 corresponds to h0 in Figure 2, h01 corresponds to h1 in the figure, g00 corresponds to g0 in the figure, and g01 corresponds to g1 in the figure. Subsystem1, Subsystem2, Subsystem3, Subsystem4 are adaptive filters. The order of the adaptive filters of Subsystem2 and Subsystem3 is 1/20 of the order of Subsystem1 and Subsystem4. The expected signal is provided by the sine wave1 module, and the input signal is composed of the superposition of Sine wave2 and Random Bitstream. The modules required by the system are all directly called modules in DSP builder. Subystem2 is a 7th-order NLMS algorithm adaptive filter, and its block diagram is shown in Figure 4. If you want to increase the convergence speed, you can add delay modules, adaptive subsystem modules, and adder modules, but it will consume more hardware resources.

The adaptive filter module is mainly composed of a delay unit, a weight update subsystem, an adder module, and a multiplier module. It performs adaptive filtering on the extracted signal. [page]

The unit impulse response of the FIR filter is of finite length, and its z transform is . The analysis and synthesis filter system is mainly composed of delay units, adders, and adder modules. The analysis and synthesis filters cannot have the ideal characteristics of sharp cutoff, and must be approximated by increasing the order. The analysis filter subsystems h00, h01, h10, h11, and the synthesis filter subsystems g00 and g01 all adopt cross-sectional structures.

The weight update subsystem module is mainly composed of multipliers, dividers, adders, delay units, bus type conversion modules, etc. This subsystem mainly completes the weight update of the filter. w(k+1)=w(k)+μ／γ+xT(k)x(k)e(k)x(k) operation and wi(k)xi(k) operation.

4 Simulation

Matlab's Simulink environment has a powerful graphical simulation verification function. After designing a new model with the DSP Builder module, you can directly perform algorithm-level and system-level simulation verification in Simulink. The Simulink simulation of this design is shown in Figure 6. The output signal contains burrs, which means that there is still a certain steady-state error between the output signal and the expected signal. You can increase the order of the filter or modify the step size control parameter μ to achieve better results.

Running Signal Complier can convert the module file (.mdl) passed by Simulink into a VHDL file passed by the hardware description language; running Testbench (test platform) can convert Sine wavel, Sinewavel+noise, and Clock into test files for the HDL simulator ModelSim. As shown in Figure 7, the output signal Sine out gradually tends to be stable and approaches the expected signal sine wavel, so the design result meets the requirements and can realize the adaptive process.

5 Conclusion

This article only designs the FPGA implementation of two sub-band adaptive filters from the hardware perspective. Due to the non-ideal characteristics of the decomposition filter bank, it is necessary to adopt inter-sub-band filtering, which can greatly improve the convergence speed. The design and research process of the sub-band adaptive filter is relatively complicated. Here we explain the main design research ideas. In view of the relatively small order of the adaptive filter in the design, it has a certain impact on the steady-state error of the adaptive filter. By increasing the order of the adaptive filter, analyzing and synthesizing the order of the filter and the number of bits of data, the accuracy can be improved.