NASA and Microchip Collaborate on Space-Grade High-Performance Processors

NASA's Jet Propulsion Laboratory in Southern California has selected Microchip to develop a high-performance spaceflight computing (HPSC) processor that will provide at least 100 times the computing power of current spaceflight computers. This critical capability will advance all types of future space missions, from planetary exploration to lunar and Martian surface missions.

“This cutting-edge spaceflight processor will have a huge impact on our future space missions and even technology here on Earth,” said Niki Werkheiser, director of technology maturation for the Space Technology Mission Directorate at NASA Headquarters in Washington. “This work will expand capabilities of existing spacecraft and add new capabilities, and ultimately could be used by nearly all future space missions, all of which benefit from more powerful processors.”

Microchip will build, design and deliver the HPSC processor over three years, with the goal of using it in future lunar and planetary exploration missions. Microchip's processor architecture will make computing power scalable based on mission needs, significantly improving the overall computing efficiency of these missions. The design will also be more reliable and more fault-tolerant. The processor will enable spacecraft computers to compute 100 times faster than today's most advanced space computers. As part of NASA's ongoing commercial partnership efforts, the work is under a $50 million contract, with Microchip providing significant research and development support.

“We are delighted that NASA has selected Microchip as its partner to develop the next generation of space-grade computing processing platforms,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “We are investing with NASA in a new trusted and transformative computing platform that will deliver comprehensive Ethernet networking, advanced AI/ML processing and connectivity support, while providing unprecedented performance gains at low power, fault tolerance and a secure architecture. We will foster an industry-wide ecosystem of single-board computer partners based on HPSC processors and Microchip’s complementary space-grade total system solutions to benefit a new generation of mission-critical edge computing designs optimized for size, weight and power.”

Current space-qualified computing technologies are designed to address the most computationally intensive parts of a mission—an approach that results in over-design and inefficient use of computing power. For example, a Mars surface mission requires high-speed data movement and intensive computation during a planetary landing sequence. However, routine mobility and science operations require fewer computations and tasks per second. Microchip's new processor architecture provides the flexibility for processing power to rise and fall based on current operational requirements. Certain processing functions can also be shut down when not in use, reducing power consumption. This capability will provide significant power savings and improve overall computing efficiency for space missions.

"Our current spaceflight computers were developed 30 years ago," said Wesley Powell, NASA's chief technologist for advanced avionics. "While they have performed well on past missions, future NASA missions will require significant improvements in onboard computing power and reliability. New computing processors will provide the advances in performance, fault tolerance and flexibility needed to meet future mission demands."

Microchip's HPSC processor could be useful to other government agencies and for other types of future space missions to explore our solar system and beyond, from Earth science to Mars exploration and lunar missions. The processor could potentially be used in commercial systems on Earth that require edge computing needs similar to those of space missions and the ability to ensure safe operation if one component of the system fails. These potential applications include industrial automation, edge computing, time-sensitive Ethernet data transmission, artificial intelligence, and even IoT gateways, which connect a variety of communication technologies.

In 2021, NASA solicited proposals for a trade study for an advanced radiation-hardened computing chip with the goal of selecting a vendor for development. The contract is part of NASA's High Performance Space Computing program. HPSC is led by the agency's Space Technology Mission Directorate's Game Changing development program, with support from the Science Mission Directorate. The project is led by JPL, a division of Caltech.