PCI interface design based on EP2SGX series FPGA

0 Introduction

In modern radar data processing systems and other application systems, traditional ISA, EISA and other buses have gradually failed to meet the requirements of high-speed data transmission. The PCI local bus has become the mainstream bus for most systems with its advantages of high performance, low cost, ease of use and adaptability. The commonly used 33 MHz, 32-bit PCI bus has a peak transfer rate of 132 MB/s. The PCI bus interface is relatively complex compared to other bus interfaces. It has strict synchronization timing requirements, and in order to achieve plug-and-play and automatic configuration, there are many configuration registers in the configuration space of the PCI bus that need to be set. Based on a brief introduction to the PCI bus and its characteristics, this article introduces how to use FPGA to design the interface circuit of the PCI bus, and gives some issues that should be paid attention to when designing the PCI bus interface.

1 PCI bus and data transmission specifications

PCI bus signals can be divided into several types as shown in Figure 1. Among them, 64-bit bus extension signals, resource latch signals and boundary scan signals are optional.

Data transmission on the PCI bus is based on a burst transmission mechanism. A burst transmission includes an address phase and one or more data phases. Basic PCI transmission is controlled by FRAME#, IRDY#, and TRDY# signals. When the data is valid, the data resource needs to unconditionally set the xRDY# signal (IRDY# for write operation and TRDY# for read operation). The receiver can send its xRDY# signal at the appropriate time. The first clock rising edge after the FRAME# signal is valid is the beginning of the address cycle, at which time the address information and bus command are transmitted. The next clock rising edge starts one (or more) data cycles. When IRDY# and TRDY# are valid at the same time, data is transmitted between the master and slave devices. During this period, the master device or the slave device can insert a wait cycle by using the invalidity of IRDY# and TRDY# respectively. PCI bus transmission includes three contents: read, write, and abort. The timing diagrams shown in Figures 2 and 3 show the transmission process of PCI bus read and write operations.

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2 Design considerations and chip selection

At present, there are two main ways to implement the PCI interface: using a dedicated interface chip and using a programmable device. Dedicated chips such as PLX's 9050 can realize the complete PCI master module and target module interface functions, and convert the complex PCI bus interface into a relatively simple user interface. The disadvantage is the lack of flexibility. Users may only use part of the PCI interface functions, resulting in a certain waste of logic resources. The advantage of using FPGA lies in its flexible programmability. First, the PCI interface can be optimized according to the card function without having to implement all PCI functions, which can save the system's logic resources. Secondly, other user logic on the PCI card can be integrated with the PCI interface logic on one chip to achieve a compact design. Moreover, when the system is upgraded, it is only necessary to redesign the logic of the programmable device without updating the PCB layout.

The PCI bus is a synchronous bus with strict timing requirements, such as: Tval is a maximum of 11 ns, Tprop is a maximum of 10 ns, Tsu is a minimum of 7 ns, and Th is 0 ns. In addition, the PCI bus interface also requires a certain number of macro cells and I/O pins. In this design, in order to simultaneously realize other logic functions such as optical fiber data transmission, an FPGA chip model EP2SGX90EF1152 from the StratixIIGX series of ALTERA was selected. The main performance of this chip is as follows: 90,960 logic cells on the chip; 4.5 Mb of RAM resources; support for 12 high-speed serial transceiver channels, each with a transmission rate of up to 6.375 Gb/s; interface level support: LVTTL, LVDS, LVPECL. 3.3-V PCI and many other I/O standards. The EP2SGX series chip has a dedicated area (Bank) that supports PCI electrical characteristics, which is very suitable for the development of PCI interfaces.

3 PCI interface design and implementation

This design uses ALTERA's QuartusIl7.2 software and hardware description language, adopts a top-down design method to design the logic of the PCI interface, and uses QuartusII software to perform functional and timing simulation on the design.

The specific design process is as follows: First, consider the overall situation: the PCI interface is a functional module embedded in the FPGA, with the inner side facing the user logic and the outer side connected to the PCI bus through the chip's I/O pins. On the user side, it is necessary to convert the complex PCI bus commands into a command format similar to the ISA bus that is easy for users to use, separate the address line from the data line, and generate separate read and write control signals. Secondly, according to the overall requirements, the top-level design and internal module division are carried out. Finally, the specific functional modules are implemented by software programming and functional simulation is performed.

The overall block diagram of the PCI interface in this design is shown in Figure 4. As shown in Figure 4, the PCI interface is mainly composed of modules such as address/command latch and decoding, internal communication, external communication and bus state machine, and interrupt processing.

3.1 Address/Command Latching and Decoding

Since the PCI bus is an address and data multiplexed bus, the address and data need to be separated during use. First, the 32-bit address/data bus on the PCI bus needs to be latched. Decoding is to identify the PCI bus command signal CBE[3.0] and IDSEL signal from the host, and send configuration space read and write operation, I/O read and write operation, memory read and write operation and other signals to the internal logic accordingly.

3.2 External Communications

The external communication interface mainly completes the response to the PCI bus and sends the corresponding signal. For the write operation, the interface sends the DEVSEL# signal to respond to the PCI FRAME# signal to complete the handshake. The PCI protocol stipulates that the address/data bus and the command/byte enable bus are parity checked during the transaction. During the read transaction, the interface is required to drive the PAR signal line; during the write transaction, the target will calculate the parity on AD[31. 0] and CBE[3. 0] and send the PERR signal to the PCI.

3.3 Internal Communication

The internal communication interface mainly produces a set of signals facing the user end for easy use by users, including reset signal, separate read and write signals, address bus, and 32-bit data read and write bus.

3.4 Bus State Machine

This module is the key part of the original design. Its main function is to generate the total timing according to the PCI protocol to control the bus transaction. The bus state machine mainly includes the bus idle state, bus docked state, master device data transmission state, slave device data transmission state, configuration space read and write state, target I/O space read and write state, master device read and write state, bus flip state, data transmission termination state, etc. The above states are mainly based on the input PCIRST, FRAME#, IDSEL, CBE [3. 0], GNT#, IRDY#, TRDY#, STOP# and other signal changes for state conversion.

3.5 Interrupt Processing

This module mainly implements the input processing of various external interrupt sources, the control and management of the interrupt enable register and the interrupt status register, the output processing of the INTA# signal, etc. [page]

4 Use of tool software in PCI bus debugging

WinDriver software was used in the debugging process of the board. This software is a tool produced by Jungo Corporation of the United States for writing drivers. It is a development tool mainly for PCI, ISA, and USB. This software is very convenient for debugging PCI boards. Users can control PCI devices to read and write without complex programming, so that the performance of the board can be tested when the hardware is just designed and debugged. The testable functions include VenderID, Device ID identification, base address allocation, interrupt allocation, I/O port read and write test, etc.

In addition, the SignalTap embedded logic analyzer software that comes with the Quartus software was also used during the debugging process . This tool software only needs to connect the JTAG port to the debugging computer through a programming cable to collect various signal waveforms online to verify whether the logic design is correct.

5 PCI interface board design experience

The designed CPCI board has been tested and verified many times, and the configuration space access, I/O space access, external interrupt and other functions are all correct. It has been successfully applied to products. The following is a brief introduction to some of the experiences in the design and development process.

(1) Issues that require attention in PCI interface board design

① Some signals on the board must be connected to a 10 Ω terminal resistor in series near connector J1. The signals that must be terminated with resistors are: AD[31:0], C/BE[3:0], PAR, FRAME#, IRDY#, TRDY#, STOP#, LOCK#, IDSEL#, DEVSEL#, PERR#, SERR#, RST#, INTA#. The resistor should be placed within 15.2 mm from the PCI signal connector pin to reduce the impact of the signal on the backplane after the board is terminated. The signals that do not require terminal resistors are: CLK, REQ# and GNT#. In actual design, the signals must be terminated according to the above requirements, otherwise the PCI bus will not work properly.

②The length of the signal line from connector J1 to the termination resistor should not exceed 15.2 mm.

③ The length of the signal line from the connector through the termination resistor to the FPGA should not exceed 38.1 mm.

(2) Simplified design of configuration space

The configuration space of PCI bus is 2.56 bytes. In design, only the parameters used need to be configured. Generally, the configuration of registers such as VenderID, DeviceID, CommandStatus, RevisicmID, ClassCode, HeaderType, InterruptLine and InterruptPin can meet the requirements of most occasions.

(3) Simplified design of bus commands

The PCI specification specifies 16 bus commands, and designers only need to respond to useful commands. Simplifying bus commands can reduce the types of bus conversations, thereby reducing the complexity of hardware design. Generally speaking, as long as there are configuration space reads and writes, I/O space reads and writes, and memory reads and writes, general use can be met.

6 Conclusion

This article introduces the design technology of implementing PCI interface on StratixⅡGX series FPGA. It has strong flexibility and can be easily transplanted to other programmable devices. It has certain versatility. With the continuous development of computer technology, computer bus has gradually developed into PCI-X bus with higher bandwidth and frequency and PCI-Express bus with 2.5G transmission rate based on PCI bus. From the current development trend, PCI-Express bus is getting more and more widely used and will become the next generation bus standard.