Gigabit Ethernet Implementation Solution Based on Altera FPGA

1 Introduction

As system equipment continues to develop towards miniaturization, integration, and networking, embedded development has become the forefront of new technology development, changing the overall structure of the system. FPGA has become the best platform for embedded development due to its own characteristics. Altera has launched a new embedded development system based on its latest generation of high-end devices, which can realize an embedded development system with a soft-core niosII 32-bit processor as the core.

In CVCLONE II, A1tera integrates a complete Gigabit Ethernet hard core, which includes MAC module and optional physical layer PCS module and PMA module, among which MAC module supports 10/100/1000 Mb/s. Altera's SOPCBuilder tool provides the ability to quickly build SOPC system, which can include one or more CPUs, memory interfaces, peripherals and system interconnection logic.

2 Gigabit Ethernet Technology Introduction

Ethernet technology is a widely used network technology today. Gigabit Ethernet technology inherits many advantages of previous Ethernet technology and has many new features, such as transmission media including optical fiber and copper cable, using 8B/10B encoding and decoding scheme, adopting carrier extension and packet burst technology, etc. It is precisely because of its good inheritance and many excellent new features that Gigabit Ethernet has become the mainstream solution for local area networks.

Gigabit Ethernet uses all the technical specifications specified in the original Ethernet standard, including CSMA/CD protocol, Ethernet frame, full duplex, flow control and management objects defined in IEEE 802.3 standard. The key technology of Gigabit Ethernet is the implementation of Gigabit Ethernet MAC layer and Ethernet interface. With the popularization of multimedia applications, Gigabit Ethernet will inevitably be widely used.

3 Altera's Gigabit Ethernet Solution

3.1 IP core support

Altera provides a parameterizable Gigabit Ethernet megacore solution. This solution can work on Altera's Arria GX, CycloneII, and CycloneIII series FPGAs and can be configured to include one or more of the MAC, PCS, and PMA modules, configuration options, and corresponding interface standards.

The functions of the Gigabit Ethernet IP core are described as follows:

(1)Support IEEE 802.3 standard.

(2) 10/100/1 000 Mb,s Ethernet media access control supports half-duplex and full-duplex working modes.

(3) Multi-channel MAC, supporting up to 24 ports.

(4) Ethernet physical layer coding sublayer 1000BASE-X/SGMII standard auto-negotiation.

(5) The interface is easy to use.

For the implementation of the Gigabit Ethernet controller, the configuration in row 1 of the table is used. The Gigabit Ethernet Media Controller Core (GEMAC) is a parameterizable megacore solution for 1 Gb/s Ethernet media access controller functionality.

3.2 FPGA-based Gigabit Ethernet MAC controller implementation

3.2.1 Overall design plan

The FPGA design of the Ethernet controller includes the FPGA design of the Ethernet MAC sublayer, the interface design between the MAC sublayer and the upper layer protocol, and the GMII interface design between the MAC and the physical layer (PHY). The overall structural design block diagram of the Ethernet controller is shown in Figure 1. The entire system is divided into a MAC module, a host interface module, and a management data input and output module. Among them, the MAC module mainly performs flow control in full-duplex mode, and the MAC frame realizes the sending and receiving functions. Its main operations include the encapsulation and unpacking of the MAC frame and error detection. It directly provides a parallel data interface to the external physical layer device. The physical layer processing directly uses commercial gigabit PHY devices. The main development focuses on the research of the MAC controller.

The management data input and output module provides a standard IEEE802.3 media independent interface, which can be used to connect the link layer and physical layer of Ethernet. The host interface provides an interface between the Ethernet controller and the upper layer protocol (such as TCP/IP protocol) for sending and receiving data and setting various registers in the controller. [page]

3.2.2 Interface Description

The interface connection between the modules of the entire system is shown in Figure 2. Among them, PCS and PMA represent the physical coding sublayer and physical medium access layer of the physical layer respectively.

(1) Provides seamless connection with Ethernet physical layer (PHY) devices through the MII/GMII interface.

(2) Support RGMII interface in Gigabit mode.

(3) The optional management data input/output module provides management information to the Ethernet PHY.

(4) Provide users with an 8-bit/32-bit interface based on Aalon-ST.

(5) Optional integrated physical media intervention module.

3.2.3 Gigabit Ethernet IP Core

Altera provides a tri-mode Ethernet MAC controller IP core that can implement single or multiple Gigabit Ethernet links and can be connected to any Ethernet port through a switch or router. Its configuration interface is shown in Figure 3.

The entire configuration interface can configure the IP core to the required mode and set the IP core parameters. The IP core is set to a Gigabit Ethernet MAC module, and a FI-FO module is provided internally. The optional PCS module is provided by the PHY device. This interface is divided into 4 configuration pages, which are described as follows:

• Core Configuration: Core configuration options, configure Ethernet function modules, whether to include PCS modules and FIFO modules, configure interface types, number of ports, etc.
• MAC Options: MAC configuration options, configure MAC module functions;
• FIFO Options: FIFO memory options, you can set the FIFO memory type and memory data length;
• PCS/SGMII Options: Physical media access layer module configuration page, configure the physical layer.

• The corresponding interface signals include: control interface signals, reset signals, MAC system end signals (including receiving interface signals and transmitting interface signals), MAC Ethernet end signals (including GMII module signals and PHY management interface signals).

Table 1 describes the GMII module signals and interface signals on the MAC Ethernet side. For other signals, refer to the Gigabit Ethernet User Manual. The receiving signal of the GMII module is generally directly connected to the PHY device and is responsible for data interaction with the PHY device. Its signals correspond to the PHY device interface one by one, as listed in Table 1.

[page]

4 Physical layer (PHY) devices

The physical layer devices supported by Ahera's Gigabit Ethernet MAC core by default include National DP83848C supporting 10/100 Mb/s, National DP83865 supporting 10/100/1 000 Mb/s, Marvell 88E1145 and Marvell 88E1111 supporting dual physical layers and 10/100/1 000 Mb/s. Here, National DP83865 is selected as the PHY device.

The connection between the MAC core and the Gigabit PHY device through the GMII interface is shown in Figure 4.

The DP83865 is a full-featured physical layer transceiver from National Semiconductor that integrates the PMD sublayer to support 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet protocols with ultra-low power consumption and a 3.3V or 2.5V MAC interface.

5 Development Environment

Using Ahera's powerful SOPC Builder system development tool and QuartusII software design, the SOPC design process based on QuartusII and niosII is shown in Figure 5. The SOPC development process adds more customization steps of the processor and its peripheral interfaces and software development steps (bold frame) than the FPGA development process (thin frame). These newly added steps can be easily completed with the assistance of SOPC Builder and niosII IDE tools.

6 Conclusion

The Gigabit Ethernet system can directly send the processed high-speed signal from the network port to the remote processing computing platform, saving power amplifiers and high-frequency cables, reducing investment, enhancing the integration and reliability of the system, making it easier for designers to debug, and making the interface more versatile and extensible.