High-speed CCD sound and light signal acquisition system based on FPGA and USB2.0

0 Introduction

In the field of modern communications and radar, broadband, high gain, and real-time parallel processing are important features of modern receivers. Therefore, this kind of acousto-optic processing system with high-speed parallel processing capability and unique large bandwidth performance has huge potential advantages. In addition to the characteristics of broadband, high gain, and real-time parallel processing, the receiver based on acousto-optic devices also has the advantages of large capacity, small size, and low power consumption. Therefore, it is of great significance to use acousto-optic signal processing technology to solve the problems of bandwidth, high gain, and real-time parallel processing. The design of the acousto-optic signal acquisition system is one of the keys to the entire acousto-optic system. Here, a high-speed CCD acousto-optic signal acquisition system based on FPGA and USB 2.0 is designed to provide a hardware platform for acousto-optic signal acquisition.

1 System Overview

The block diagram of the sound and light signal acquisition system is shown in Figure 1. The system mainly consists of four parts: CCD sound and light signal acquisition module, A/D conversion module, FPGA drive and control module and USB interface transmission module.

After the system is powered on, the USB device completes the initialization setting and acquisition control of FPGA data acquisition parameters according to the command of the host computer. RL2048P works under the strict control of the drive timing. The collected analog signals are cached in the FIFO configured inside EP2C35 after the correlated double sampling and analog/digital conversion of the dedicated CCD signal processing chip AD9822. Then, when the data in the FIFO reaches 2 048 B, the data is asynchronously written to the USB controller CY7C68013A. Since the USB is set to automatic IN mode, the data in the FIFO can be directly transferred to the hard disk file of the PC host computer, thus completing the acquisition, transmission and storage of CCD sound and light signals.

2 Design of system modules

The system modules are designed as follows:

The FPGA drive and control module system uses Altera's CycloneⅡ series. EP2C35F672C6 chip, with high cost performance and rich logic resources, can meet the requirements of the system. There are 4 PLLs, 33 216 LEs, 48 ​​KB memory resources, which can be configured into various modes of ROM, RAM and FIFO, 35 18×18 dedicated multipliers. The main functions of FPGA are to generate RL2048P drive timing, control AD9822 sampling and serial programming of its registers, configure internal FIFO cache data and communicate with USB interface, and transmit data to the host computer.

The CCD acoustic and optical signal acquisition module uses the RL2048P linear array CCD of PerkinElmer. This chip is mainly used for high-speed signal acquisition, with 2,048 effective pixels, high sensitivity, large dynamic range, wide spectral range, etc. The maximum operating frequency is 40 MHz, and the system is designed for 10 MHz. The timing drive output of EP2C35 is 3.3 V LVTTL level, which cannot directly drive RL2048P (multi-level requirements). Therefore, DG642 and 74FCT16244TV chips are used to complete the level conversion and enhance the driving ability. Figure 2 is the RL2048P drive timing diagram; Figure 3 is the QuartusⅡ simulation of the drive timing written in Verilog HDL. From the comparison, it can be seen that the design can fully meet the strict requirements of the timing.

[page]

The A/D conversion module AD9822 is a dedicated CCD signal processing chip of ADI. It integrates CDS, PGA, 14-bit ADC , dark level automatic calibration, bias voltage control and serial interface functions, and the sampling speed is up to 15 MHz. The falling edge of ADCCLK outputs the high 8 bits of data, and the rising edge of ADCCLK outputs the low 6 bits of data. The AD9822 sampling control timing and register programming are implemented by EP2C35, which is synchronized with the output signal of RL2048P to ensure the correctness of the collected data. The correlated double sampling mode can suppress the reset noise of CCD. The registers of this system are set to 0x0058, 0x10C0, 0x2000, and 0x50FF respectively.

The USB interface transmission module USB 2.0 protocol has a transmission speed of up to 480 Mb/s, and has the advantages of simple interface and low bit error rate, which can meet the needs of high-speed transmission of the system. The new generation of low-power CY7C68013A chip from Cypress is selected, and the corresponding development kit and development documents are relatively complete, which shortens the development cycle and reduces the development difficulty. In order to ensure the speed of data transmission, CY7C68013A works in SlaveFIFO mode, and can complete data transmission with FPGA without the CPU intervention of EZ-USB FX2LP. The communication between EP2C35 and CY7C68013A adopts the asynchronous mode in Slave FIFO mode, writes data to the large endpoint EP6, configures it as a 512 B quadruple buffer, batch AUTO IN transmission mode, and automatically submits 512 B data each time. Figure 4 shows the interface connection between EP2C35 and CY7C68013A.

3 System Software Design

System software design includes:

Firmware design The main function of the device firmware is to control CY7C68013A to receive and process the requests of the USB driver. Such as requesting device descriptors, requesting or setting device status, requesting or setting device interfaces and other USB 2.0 standard requests; assisting hardware to complete device re-enumeration, endpoint configuration, control and monitoring USB activities, and data exchange with peripheral circuits according to the commands of the PC host. Cy-press provides users with a firmware program framework, which is a highly versatile modular program. Based on the framework, users only need to write Function. c files to complete USB function development. It mainly includes: initialization of Slave FIFO mode and user-defined requests.

The driver development system includes two USB drivers: one driver is dedicated to download the chip firmware program CCDloader.sys, and the other general driver ccdusb.sys is used to realize the communication and control between USB devices and applications. The chip firmware program is on the host. When the system is powered on, the former downloads it to the chip's RAM and is executed by the enhanced 8051 microprocessor . When the firmware download is completed, a disconnection and reconnection is simulated . At this time, the downloaded firmware responds to USB enumeration and loads the USB device general driver. The USB driver is of WDM type and can be developed using Windows DDK, WinDriver, and DriverStudio.

The main task of application development is to communicate with the USB driver and control the process of sound and light signal acquisition. Here, Visual C++6.0 is used for program design. The CyAPI control function class provides a very fine control interface for the FX2LP series USB interface chip. You only need to add the header file CyAPI.h and the library file CyAPI.lib to the application to call the corresponding control function, open the USB device to read the data and store it in the CcdData.txt file on the host hard disk. [page]

4 Experimental data analysis

Using the TEKTRONIX oscilloscope, the RL2048P output signal after DC isolation was tested and analyzed under various experimental conditions. As shown in Figure 2, VOUT is the pixel output signal. Each pixel output signal has a synchronous reference signal at the beginning, and the latter part is the effective signal output. Since the CCD output signal is a negative polarity signal, the effective signal value is negative relative to the reference signal.

Figure 5 shows the output of RL2048P under full darkness. Since there is no light on the photosensitive surface, only dark level signal is output, so the effective signal of the pixel output is almost zero. Figure 6 shows the output of RL2048P under weak light condition, and the effective signal amplitude has changed. Figure 7 shows the output of RL2048P under full brightness condition, and the effective signal has reached the saturation value. The actual output of RL2048P is consistent with the theoretical analysis and works normally. The acoustic and optical signals are shone on the CCD through the opaque shielding plate with a hole in the middle, and the application software is used for data acquisition. 8192 pixel points, i.e. four frames of CCD data, are continuously extracted from the CCD Data.txt data file, and the Matlab software analysis is shown in Figure 8.

The position with light irradiation corresponds to the highest position, and the measured data is consistent with the theoretical value. Related experiments were also conducted under other conditions, and the results were basically consistent with the theory. Due to space limitations, this article does not provide a detailed introduction. The experimental results show that the system is fully functional and can achieve high-speed acquisition, transmission and storage of acoustic and optical signals.

5 Conclusion

The system uses on-site FPGA as the hardware design core and uses Veritog language to describe the hardware, making the system more flexible, online programmable, and easy to expand and upgrade. The CCD drive timing here adopts a new method combining state machine and frequency division. The actual test drive waveform is stable and has no burrs, and the CCD output signal quality is high. USB is used in Slave FIFO high-speed transmission mode, which meets the requirements of high-speed CCD sound and light signal acquisition, and has the characteristics of real-time, high speed, stability, and reliability.