Computer Organization Principles Bus Design

We know that a computer is composed of five major components: arithmetic unit, memory, controller, input device and output device. This concept is relatively abstract. To put it simply, the CPU includes the arithmetic unit and the controller, the memory refers to the memory, and the input and output devices refer to the keyboard and the display respectively. These components of the computer need to work together to complete information processing. So, how do these major components communicate with each other? It depends on the system bus, which is also the focus of our article.

Understanding the bus

A bus is a path that connects two computers or multiple functional units together and allows them to exchange data with each other. A bus can also connect computers and external devices together. The bus is a very important component of a computer system. You need to know the following concepts.

Bus width: The width of the bus is generally defined by the number of parallel data paths. The bus widths are generally 8 bits, 16 bits, 32 bits, and 64 bits. The most commonly used bus now is the 64-bit bus. A 64-bit bus can transmit 64 bits, or 8 bytes of information, at a time.

Bandwidth: Bandwidth is a measure of the speed at which data can be transferred on a bus. Increasing the number of parallel paths while keeping the data transfer rate constant can increase the bandwidth of the bus.

Latency: Latency is the time interval between a request for data transfer and the actual data transfer.

Bus Classification

Below we mainly introduce two types of buses, one is the on-chip bus and the other is the system bus. The on-chip bus generally refers to the connection inside the CPU chip, between registers, and between registers and the arithmetic unit ALU.

The system bus mainly refers to the information transmission medium between major components such as CPU and memory, memory and IO devices, CPU and IO devices, etc. The system bus is mainly divided into the following three categories according to the different information transmitted.

Address Lines

Data cable

Control Line

Let's take a closer look at these three types of buses.

Address Bus

The address bus is mainly used to transmit the address of source data or destination data in the main memory unit.

The CPU specifies the location of storage units through the address bus. The CPU can address as many storage units as the information that can be transmitted on the address bus.

In the above figure, the information exchange between the CPU and the memory passes through 10 address buses. The data that can be transmitted on each line is 0 or 1, so the data transmitted between the CPU and the memory at one time in the above figure is 2 to the tenth power.

Therefore, if the CPU has N address buses, then we can say that the width of this address bus is N. In this way, the CPU can search 2 to the power of N memory cells.

Data Bus

As the name suggests, the data line is the number of bits of data transmitted at one time, and the number of bits of the data bus is the data bus width.

Data transfer between the CPU and memory or other components is accomplished by the data bus. The width of the data bus determines the data transfer speed between the CPU and the outside world. 8 data buses can transfer an 8-bit binary data (i.e., one byte) at a time. 16 data buses can transfer two bytes at a time, and 32 data buses can transfer four bytes at a time. . . . .

Control bus

The control bus is a transmission line that sends control signals on the bus. Common control signals include: clock (synchronous operation), reset (initialization operation), interrupt request/response, memory read and write, IO read and write, etc.

The control between the CPU and other components is accomplished through the control bus. The number of control buses means the number of ways the CPU can control external devices. Therefore, the width of the control bus determines the CPU's ability to control external components.

Connection method based on computing unit

In the early stages of the Internet, most buses used decentralized connections (there is also a bus connection, which will be discussed later). This connection method is shown in the following figure

As can be seen from the figure, the arithmetic unit is the core part of this distributed connection. This connection method will cause problems. When your CPU is busy calculating, information exchange between IO and memory occurs. At this time, your arithmetic unit, that is, CPU, has to stop, which leads to the interruption of the operation of the arithmetic unit and seriously affects the working efficiency of the CPU.

Imagine that when you are writing an article, your partner asks you: Why didn’t you talk to me today? So you have to put down your work and chat with her; after you deal with her emotions, you continue to write for 5 minutes, and then your reader writes a long article to ask you a question. You can’t just reply at this time, so you have to put down your writing again and help him solve the problem. It can be seen from this that your writing efficiency will be high? The same is true for CPU.

Of course, you can also choose to enter focus mode and not reply. This depends on the priority of the matter, and the same goes for the CPU.

Bus Design

Storage-based connection

Later, in order to improve this situation, a memory-centric structure emerged, which is shown below

As you can see, this connection method is centered on the memory. The functions of the main components involved in the figure are as follows

Input devices convert commonly used information into data forms that can be recognized by machines. Common input devices include keyboards and mice.

Memory is used to store instructions and data

The operator is used to perform arithmetic and logical operations and temporarily store the results of the operations in the operator.

The controller is used to complete the command and control of the input, operation and processing of program and data.

The conversion process of the output device is the reverse process of the input device, that is, converting the calculation result into a form that people can understand.

Since the arithmetic unit and the controller are closely related in circuit structure, they are usually collectively referred to as CPU, input/output devices are collectively referred to as IO devices, and storage is memory.

Therefore, the composition of modern computers is generally CPU + memory + input/output devices.

By using this connection method, the information exchange between IO and main memory can be done without going through the arithmetic unit, and with the development and maturity of interrupt and DMA technology, the CPU efficiency is greatly improved.

However, this method still cannot solve the flexibility of the connection between IO devices and the host, because when we want to add an IO device, this connection method cannot handle it, so the bus connection method appears.

CPU-based dual bus connection

The bus uses a connection method shared by multiple IO components. The bus is actually composed of many transmission lines, each of which can transmit binary data one bit at a time. For example, 16 transmission lines can transmit 16 bits of binary code at the same time.

The following is a dual bus structure centered on the CPU

The connection method shown in the figure above is a bus connection method, which connects various components to a set of common transmission lines. From the figure, we can understand the concept of dual buses: one set of buses connects the CPU and memory, called the storage bus; the other set is used to establish a channel for exchanging information between the CPU and various I/O devices, called the IO bus.

This connection method also has problems. When multiple components are connected to the bus, if two or more components send messages at the same time, signal conflicts will inevitably occur, resulting in invalid transmission. Therefore, only one component is allowed to send a message at the same time, but multiple components can receive messages.

Single bus structure design

If the CPU, main memory and IO devices are all connected to a set of buses through IO interfaces, a single bus connection is formed.

Think about a question here. What do you think is the biggest difference between the single-bus connection method and the CPU-based dual-bus connection method?

In the CPU-based dual-bus connection mode, the interaction between the CPU and the IO bus requires the participation of the CPU, and the interaction between the CPU and the memory also requires the participation of the CPU, so the CPU is working all the time. This is also fortunately the CPU, otherwise anyone else would be exhausted.

Single bus connection, because the CPU, memory and IO are all on the same bus, the interaction between memory and IO does not require the participation of the CPU, which is the biggest change. This connection method also has problems, because there is only one set of buses, when each component needs to exchange information, conflicts will occur, so in this design, it is necessary to set the bus occupancy priority so that each component can occupy the bus in order of priority. This is also the real reason why locks are used as thread safety in programming languages.

Another problem is that the CPU does not interact directly with the memory, which greatly affects work efficiency.

Memory-centric dual-bus architecture

Another connection method is a dual bus structure centered on the memory, and its design is as follows

This bus design structure is very comfortable. It adds a storage bus between the CPU and the memory on the basis of the above single bus structure. When the IO uses the system bus frequency at a high frequency, the CPU and the memory can interact through the storage bus, which greatly speeds up the system work efficiency and reduces the bus overhead. It also retains the feature that the memory and IO do not need to go through the CPU when interacting.