Application of BIST on SoC Embedded Microprocessor Core

introduction

With the continuous development of science and technology, the manufacturing process and design level of integrated circuits have been rapidly improved, and designers can integrate very complex functions into silicon chips. The system of multiple chips on the PCB board is integrated into a chip. This chip is a system-level chip, namely SoC (System on Chip). The characteristics of SoC chips are mainly two aspects: the first is its high complexity, and the second is the extensive use of reusable IP (Intellectual Property) modules. In the past, chip design often only focused on the module design of a specific function, such as compression/decompression, wireless module, network module, etc. The function of a SoC chip may be the sum of multiple independent modules. In addition, the manufacture of chips requires chemical, metallurgical, optical and other process processes, in which physical defects may be introduced, causing them to not work properly. Therefore, chip testing has become an indispensable link. Design for Test (DFT) is to consider the need for future testing at the chip design stage, making chip testing easier and more sufficient, and reducing testing costs. A SoC contains various reusable functional IP cores, among which the embedded microprocessor core is the key part, and most of them are embedded with one or more microprocessor cores to obtain the best performance. Therefore, the research on microprocessor core testability is becoming more and more urgent.

1 Traditional testing methods

Before the 1970s and 1980s, when integrated circuits were still small-scale circuits, most tests were completed by adding stimulus and probing the corresponding methods. This method is still feasible when the circuit scale is small and the frequency is not fast, but as the scale of integrated circuits grows, the functional verification content increases, or when asynchronous stimulus signals are needed, this test method has limitations. In order to improve the test coverage of fault points, automatic vector generation (ATPG) tools have emerged. Using ATPG algorithms and powerful computers, as many fault points as possible can be detected. As the scale of chips grows, the ratio of the number of chip gates to the number of pins becomes too disparate, and the method of testing only through input/output pins can hardly be applied. Therefore, another scan-based test technology, DFT, has emerged. However, when the scan chain is very long and the number is large, the test time of a single chip is still very long. At the same time, the price of advanced test instruments has risen rapidly, making the emergence of BIST (Built-In Self-Test), i.e., the on-chip test method, inevitable.

2 Several Commonly Used BIST Methods and Their Advantages and Disadvantages

On-chip testing is an effective means to save chip testing time and cost. The test speed of external testing increases by 12% per year, while the speed of on-chip chips increases by 30% per year. This contradiction further promotes the application of BIST. Due to the wide variety of IPs inside SoC chips, different BIST test methods are used for different IP cores. The advantages of using BIST technology are: reducing test costs, improving error coverage, shortening test time, facilitating customer service and independent testing. At present, the main BIST test methods are MemBIST and LogicBIST.

2.1 MemBIST

MemBIST is a test method for embedded chip memory, used to test whether the memory is working properly. There is a BISTController inside the chip, which is used to generate various modes and expected results of memory testing, and compare the read results of the memory with the expected results. MemBIST can be divided into RAMBIST and ROMBIST. Currently, the more commonly used memory BIST algorithms are March algorithm and its variants. Commonly used tools in the industry include Mentor Graphics' MBIST Architecture.

2.1.1 RAMBIST Test Structure

The data cache and instruction cache implemented by RAM use the common BIST method. Because the structures of the two RAMs are exactly the same, only one set of test circuits is used to reduce area consumption. During the test, external signals TE0 and TE1 control whether RAM1 and RAM2 are in the test state respectively. TE0 and TE1 cannot be valid at the same time. The test circuit structure is shown in Figure 1.

Under the control of the external input signal BIST, the controller generates read and write control signals, access addresses and test codes, compresses and analyzes the corresponding data of the RAM, and compares the obtained characteristic values ​​with the standard characteristic values ​​stored in the chip. The test results are reported through two I/O ports, and the preliminary fault diagnosis function is also realized. When a fault is found, the TAP controller can remove the wrong address from the chip to provide information for further fault diagnosis and repair. [page]

2.1.2 ROMBIST Test Structure

Cyclic Redundancy Check (CRC) circuit is usually used to test ROM. Although the test results of this method are very reliable, it requires reading information bit by bit, and the access to ROM is 32 bits at a time. If this method is used, a buffer mechanism is required, and the speed will be very slow. Here, parallel data compression in RAM testing is still used, and the fault coverage can meet the requirements. The test circuit is also simpler than the CRC circuit. The test circuit is shown in Figure 2.

The BIST test signal is input from the TDT port of the TAP controller and is the enable signal for the entire test circuit. After the test process is triggered, it is completed completely inside the circuit and the test result is reported through an I/O port. The multiple input register (MISR) is used as the data register of the TAP controller and is set to the initial state when the test is initialized.

2.2 LogicBIST

The LogicBIST method uses an internal vector generator to generate test vectors one by one, applies them to the circuit under test, and then generates an identification code through digital compression and identification, and compares this identification code with the expected value.

LogicBIST is usually used to test random logic circuits. It generally uses a pseudo-random test pattern generator to generate input test patterns, which are applied to the internal mechanism of the device; MISR is used as the output signal generator. Due to the structure of MI-SR and the inherent characteristics of the identification code of multiple input sequences, this is a many-to-one mapping relationship. Different input sequences may generate the same identification code after passing through MISR, which is called alias.

LogicBIST test can only get the result of whether the chip can pass the test. Once the chip fails the test, how to determine where the fault point inside the chip is? This is the diagnosis work, but LogicBIST's support for fault diagnosis is too weak. If a chip fails, it is difficult to determine where the fault point is based on the wrong identification code alone. Sometimes, the combined effect of multiple fault points inside the chip makes the identification code correct. This is called a missed test. The probability of its occurrence is very small, and there are algorithms to minimize the probability of missed tests. One method is to input the correct sequence and make a single mapping with the correct identification code. Other incorrect inputs will definitely get incorrect identification codes. This method requires specific analysis of MISR, PRRG and CUT to change their structure or the generation order of PRPG.

Conclusion

This article introduces the current status of research on the testability technology of embedded microprocessor cores on SoC chips; it introduces the technology of implanting relevant functional circuits in the circuit during design to provide self-test functions, so as to reduce the dependence of device testing on automatic test equipment (ATE). BIST technology can realize self-testing and solve the problem that many circuits cannot be directly tested (because they have no external pins).

It is foreseeable that in the near future even the most advanced ATE will not be able to fully test the fastest circuits, which is one of the reasons for adopting BIST. However, BIST also has some disadvantages, such as additional circuits occupying valuable area, generating additional pins and possible test blind spots. BIST technology is becoming an alternative to high-priced ATE, but it cannot completely replace ATE at present, and they will coexist for a long time in the future.