Design of IP core test scheme based on BIST

1 Introduction

With the development of semiconductor technology, system-on-chip (SOC) has become a mainstream technology today. SOC design based on IP reuse integrates IP cores into a system through user-defined logic (UDL) and wiring, which improves design efficiency, speeds up the design process, and shortens product time to market. However, with the increase in design scale, integration density, IP pins, and IP implantation depth, the test and verification work will inevitably be heavy. According to statistics, in SOC design, the time spent on the test and verification of various cores accounts for 60% to 80% of the entire design process. The test and verification of SOC and IP cores has become a bottleneck in the development of SOC technology. How to pass the IP core verification and test efficiently and quickly in the shortest time and integrate it into SOC has become the focus of the industry and the direction of research that urgently needs breakthroughs and realization.

The IP core types and sources of SOC based on IP core reuse are different, and even verified IP cores cannot be guaranteed to be error-free during integration. After the IP core is integrated into the SOC, its input and output ports are also embedded into the SOC, and the originally testable ports lose their original controllability and observability and become untestable.

Therefore, people have been looking for effective test and verification technology. This paper presents a method based on built-in self-test (BIST) to improve the testability of the IP core while considering the design of its test shell when designing the codec IP core.

2 Test Structure

The so-called test is the process of applying a corresponding excitation signal to the input pin of the circuit under test, then detecting the response of the output pin, and comparing the detected output pin response with the expected pin response to determine whether the circuit has a fault.

The purpose of IP core testing is to detect whether there are functional and timing errors in the IP core, so as to modify the IP core and improve the reliability of the product. Generally, the input end of the IP core is stimulated by means of access, isolation, and control to obtain a response and compare it with the expected response. The test structure of the embedded IP core is shown in Figure 1.

The test stimulus source generates the stimulus required for the embedded IP core test. The response analyzer analyzes the obtained response. If they are the same, it indicates that there is no fault. If they are different, it indicates that there is a fault. The test access mechanism is a means for the SOC to transmit data. It transmits the test stimulus to the input port of the IP core and transmits the test response from the output port of the IP core to the response analyzer. The test shell is the interface between the IP core and the access mechanism and other logic of the device; the test shell can realize the test isolation between the cores on the chip, and can also provide a test data transmission channel for the IP core.

3 Built-in self-test principle

Built-in self-test is an important method of testability design. Its basic idea is to let the circuit generate test vectors by itself, rather than applying test vectors externally, and rely on itself to judge whether the results are correct. The schematic diagram of built-in self-test is shown in Figure 2.

The test wrapper is considered in the design of the IP core. The switch between BIST and normal mode can be controlled through the outside of the test wrapper. The inside of the test wrapper often uses boundary scan modules, shift registers or multiplexers, which play the role of access, isolation and control, and can improve the testability of the IP core. However, adding a test wrapper will increase the area overhead of the IP core, so a trade-off must be made between the testability and area of ​​the IP core.

4 Implementation of built-in self-test

Controllability refers to the difficulty of driving a node to the logical state 0 or 1; observability refers to the difficulty of observing the internal node failure from the external port; testability refers to the controllability and observability of all nodes in the entire circuit. Obviously, high testability makes it easier to generate test vectors and has good test results. [page]

In order to improve the testability of IP cores, specific circuits are designed to facilitate testing. Using BIST to test IP cores generally has the following advantages: simplifying the test interface; improving test quality; reducing test costs; and improving test reliability.

The block diagram of the BIST-based encoder IP core test implementation is shown in Figure 3.

By controlling the input/output registers through the test shell, the codecs are isolated so that they do not affect each other. The normal state and the test state can be switched, which improves the testability of the IP core. The specific implementation process is as follows:

(1) Under normal conditions, the original code is input into the encoder, and the code output by it enters the decoder and is converted into the original code again;

(2) In the test state, the test vector of the test shell is input to the encoder, and the code output by it directly enters the decoder. The code output by the decoder is the test response output, which is compared with the expected value; the logical structure of the mode selection module in Figure 3 is shown in Figure 4.

In Figure 4, mod is the mode selection control terminal, and setting it to 0 is the normal state. When rood is 1, out_sel inputs the test vector, which is then output by in_tem and enters in_sel; when mod is 0, cod_out outputs outside the chip, thereby realizing the switching between the normal state and the test state. This logic circuit can be written in hardware description language. It is described as follows in VHDL: