Power Management in Complex SoC Design (Part 1)

Reducing power consumption has long been a key requirement in chip design. This requirement has become increasingly important as larger and faster integrated circuits are used in portable products. As a result, power management techniques throughout the design process are constantly being improved to ensure that all parts of the product are properly and efficiently powered while maintaining product reliability. Techniques such as multiple voltage islands and dynamic adjustment of clock frequency and threshold voltages help conserve battery energy in portable products while providing high performance.

More importantly, the growth in size and speed of SOCs has brought power challenges to a large number of designs that are not traditionally limited by power supply. In these designs, thermal dissipation and reliability issues such as electromigration and voltage drop have become extremely critical. Power issues in deep submicron designs can limit the functionality or performance of the design and seriously affect the manufacturability and yield of the chip. Higher power consumption causes the junction area to heat up, causing the transistor to operate slower and increasing the interconnect resistance. If power issues are not considered, the device performance will be lower than expected, which will reduce the device yield. In addition, higher power consumption requires more system-level measures for thermal management. Taken together, these power issues are causing

Increased SoC and system costs. Power management in the SoC design process can effectively control these costs.

Power consumption in SoC

The total power of a chip is equal to dynamic power plus static power. Dynamic power refers to the power consumed during the switching logic state transition, including the power inside the unit (internal power) and the power of driving chip nodes and external loads (switching power). Dynamic power = CV2F, where C is the load, V is the voltage swing, and F is the frequency of logic state transition. As semiconductor device structures become increasingly miniaturized, device and interconnect capacitances are reduced, and chips have achieved higher performance and lower power consumption. Larger designs and higher switching rates will lead to increased power. Static power (leakage power) refers to the power consumed when the transistor is not switching.

Static power = VISTAT Although there is leakage current in some reverse-biased diodes between the transistor drain and the substrate, most of the leakage power comes from the subthreshold current when the transistor is turned off. Since subthreshold leakage current increases as the transistor threshold voltage (Vth) decreases, it brings certain troubles. As process technology continues to develop to 130nm and below, leakage power may account for 50% of the total chip power (see Figure 1). Increasing leakage power exponentially increases reliability-related failures in the chip, even in standby mode.

As CMOS process size decreases, the main method of reducing power has shifted to reducing the supply voltage VDD. Since power is proportional to the square of voltage, reducing voltage is very effective in controlling the dynamic power of the chip. However, since the switching delay time is proportional to the load capacitance and Vth/VDD, simply reducing the supply voltage will result in a reduction in circuit speed. In order to ensure sufficient drive capability required for fast switching, Vth must be reduced in proportion to VDD, which in turn will increase leakage power. A better approach is to use a design flow that takes power management into consideration to balance timing requirements with various power consumption targets.

Power Solution

The higher the design abstraction level, the greater the impact on power consumption. For example, at the system level and algorithm level, using parallel implementation instead of serial implementation can reduce clock frequency, thereby significantly reducing power consumption. However, the low power of the parallel approach may come at the cost of increased area or reduced performance.

Take a chip for serial reception of data samples as an example to illustrate the different effects of parallel and serial architectures. By processing data samples in parallel, the clock of the chip logic circuit can be reduced from 80MHz to 10MHz, and the supply voltage can also be reduced from 1.8V to 1.25V. Parallel processing logic circuits require much more area than the same serial processing circuits, but lower voltages and operating frequencies can reduce power consumption by 75%. In some other designs, the area penalty is small while the power savings are significant, so this is a trade-off worth exploring. Figure 2 introduces several power optimization and analysis techniques that can be applied throughout the SoC design process. The power solutions covered in this article are as follows: (1) module gating clocks; (2) multiple supply voltages; (3) multiple threshold voltages; and (4) power optimization during the synthesis process, including RTL-level gating clocks.

Power Estimation and Analysis

It is useful to perform power estimation during the design process at four stages as shown in Table 1. The accuracy of the power estimation at each stage increases as the design is supplemented and library information becomes available.

&nb sp; RTL-Level Power Analysis

Early in the design flow, power analysis provides a rough estimate of the power consumption of the design. At this point, the library may not have been selected yet, so library data is limited. At this point, spreadsheet analysis can be used to find the best power-conscious library and design architecture. After the library is selected, Design Compiler and Power Compiler can be used instead of or to provide data to the spreadsheet.

The power analysis spreadsheet contains approximate gate counts and activity values ​​for each module, mW/MHz data, and associated power estimates. Analysis at this point can also help determine if a design is too power-hungry to be practical, thus avoiding weeks of work on a design that is never manufacturable.

To use the spreadsheet analysis method, it is necessary to estimate the gate count (number of library cells of each type) and activity level for each module. It is also necessary to know the energy consumed by each type of cell when switching. Data from the library vendor's manual can be used to determine the correct power-to-speed ratio (mW/MHz). The internal power consumption of each type of cell within a module can be determined by

The following formula calculates: Power consumption = number of gates × mW/MHz × activity × frequency. Adding together the power of all different types of cells within a module gives an estimate of the total internal dynamic power of the module. Before synthesis, the gate count can be estimated based on the selected architecture and the understanding of the design itself. For example, the approximate gate count can be derived from bus width, word length, control layer, and memory depth. After selecting the library, the gate count of the module can be estimated after early synthesis using the Design Compiler report-reference command, which will report the number of each instantiation of the design. A key aspect of power calculation is to specify the activity level. The gate circuits in the design have different activity levels, and the estimation can be performed with or without simulating the design to extract the switching behavior. However, after selecting the library, it is recommended to perform functional simulation to determine the switching behavior.

The switching behavior is measured in toggle rate (TR). The toggle rate is the number of times a design object (such as a node, pin, or port) switches from logic 0 to logic 1 and from logic 1 to logic 0 per unit time. For a node, if it has 50 transitions from logic 1 to logic 0 and 50 transitions from logic 0 to logic 1 in a 100ns time interval, its toggle rate is 1, indicating 1 action transition per ns. The relationship between power and transition rate can be understood as the energy that must be provided to complete the state transition of the internal circuit during the time interval between state changes, so each transition consumes power.

It is important to note that power estimates at any level of abstraction only make sense if the switching actions represent the actual working state of the chip. A common mistake is to use a vector to simulate the system startup sequence when trying to determine the activity. This activity rarely represents the actual working conditions and will result in inaccurate power estimates. Using RTL-level simulation can automatically generate a SAIF (Switching Activity Interchange Format) file, but the activity values ​​are only accurate when this vector is real. Current tools cannot automatically generate such a vector because it requires a clear understanding of the circuit substance.

Figure 3 shows the Programming Language Interface (PLI) system task that can be used in VCS to generate the SAIF file during simulation. Power Compiler provides a power_estimate feature that uses SAIF files to define libraries and constraints, and to annotate the design for power estimation. The default switching behavior of Power Compiler for unannotated ports is that each rising edge has a 1/4 probability of flipping, and this value is applied and propagated throughout the module.

Tables 2 and 3 show the estimation results using the above method. After calculating the internal power, the switching power can be estimated as 30% of the internal power. Since there is no accurate load and switching data, this value is only a rough estimate. Such an estimate is mainly used to compare the power consumption of different design schemes, rather than to predict the actual power consumption of the chip. However, as mentioned above, the approximate estimate at the RTL level can indeed provide a reference for the feasibility of the chip design in the early stage.

Leakage power can be estimated based on leakage data for each cell type. Since leakage is different in the high and low states, leakage power analysis must be performed based on the static probability of a signal being in a certain logic state. The static probability is expressed as a number between 0 and 1, and this value can be estimated based on the function of the signal. For example, a low-active reset signal will generally have a static probability (SP1) of logic "1" equal to or close to 1.0 (100%). For a data bus signal, its SP1 can usually be assumed to be 0.5 (50%) unless some architectural characteristics suggest otherwise. After the library is selected, the static probability can be calculated during simulation by comparing the time the signal is in a particular logic state to the total simulation time.

Gate-Level Power Analysis

After synthesis is complete, it is possible to get fairly accurate power estimates from Power Compiler based on the actual gate count and the activity from simulation. The inaccuracies in the estimate come from the activity and pre-placement wire load values. Accuracy can be improved by generating a SAIF file from gate-level simulation. In VCS, the same instructions as in Figure 3 can be used to generate the SAIF file, except that the first instruction should be changed to:

$set_gate_level_monitoring ("on");

It is important to emphasize again that the activity values ​​are only accurate if the simulation vectors represent the actual application behavior. The Physical Compiler tool uses the write_parasitics -distributed directive after physical optimization to improve the accuracy of loads. This directive produces annotated S

teiner paths and parasitic resistance and capacitance estimates.

After layout is complete, gate-level simulation can generate VCD (Value Change Dump) files for PrimePower analysis. The VCD file records a signal value during simulation and provides information on the design's node activity, structural data system connectivity, path delays, timing, and events.

If the chip has a large number of I/Os, switching at high speeds and driving long lines, it may become a significant factor in inaccurate estimates. If the design goal requires accurate rather than worst-case power estimates, the lumped load model of the I/O may produce overly pessimistic estimates. For more accurate results, HSPICE simulations can be performed using accurate distributed impedance models in key I/O cell types. The power of the I/O cell can then be calculated using numerical methods that determine the charge and energy of each rising/falling edge. After obtaining the current and time outputs of HSPICE, the internal power of each transient can be calculated using the trapezoidal integration method (such as in Matlab software). The I/O activity recorded in the PrimePower analysis can be used to scale the I/O power, and the total I/O power can be combined with the core power for an overall power estimate. To illustrate the differences in power estimates obtained using the estimation method described in this article at different design stages and implementation cycles, Figure 4 shows an example of a high-speed FIR filter block in a DSP design. This example demonstrates that power estimates can vary depending on the accuracy of the information provided. The figure also shows how the power estimate of the example block changes at four different stages in the design flow:

(1) Example 1 - Power estimate using worst-case switching and line load estimates;

(2) Example 2 - Power estimate using more accurate line load estimates and worst-case switching;

(3) Example 3 - Power estimate using accurate line load estimates and actual activity;

(4) Example 4 - Power estimate using accurate line load (after extraction) and actual activity based on accurate SPICE simulation.