Design of multi-button state recognition system based on FPGA

1 Introduction

As a common input peripheral, buttons are widely used in instrumentation, industrial equipment and household appliances. At present, there are two main types of button input circuits III: one is a non-scanning method that can determine the state of multiple buttons (allowing multiple buttons to act simultaneously), but it is not suitable for a large number of buttons and requires many I/0 ports; the other is a scanning array method that is suitable for a large number of buttons, but multiple buttons cannot act simultaneously. Therefore, it is necessary to develop a multi-button state recognition system that is suitable for both a large number of buttons and multiple buttons to act simultaneously, and can save the port line resources of the single-chip microcomputer (MCU). Here, a multi-button state recognition system using the VHDL language is proposed, which utilizes the characteristics of the large number of I/0 ports and programmability of FPGA to realize the recognition of 60 free button operations and simplify the control signals of the MCU.

2 System Design

FPGA is a programmable logic device with good performance, high density and great flexibility, simple and reliable peripheral circuits, etc. Therefore, the system design is composed of MCU, FPGA, buttons and other parts. 60-channel button signals enter the FPGA unit for data acquisition; FPGA processes the collected data signals, encodes and writes them into the internal FIFO. MCU extracts data from FIFO through I/O port. The module supplies power to each part through the power interface. The system design principle block diagram is shown in Figure 1.

2.1 FPGA Configuration Circuit

The FPGA uses Altera's EPF10K30ATC144. The core of the device is powered by 3.3 V, the port voltage is 3.3 V and can withstand 5 V input high level. Its operating frequency is up to 100 MHz; there are 102 available I/0 ports, each port has an input current of up to 25 mA and an output current of 25 mA; 1728 logic units (LEs) and 12,288 bits of user Flash memory, which can meet the user's small-capacity information storage needs and fully meet the system design requirements.

Since FPGA is based on RAM process technology, the device needs to load configuration data from the outside before operation, and an external memory is required to save the information. The programmable serial configuration device EPC2 is used. Its power supply voltage is 3.3 V. The OE and nCS pins have internal user-configurable pull-up resistors. The DCLK, DATA0, and nCONFIG pin signals of the FPGA all come from EPC2. After the system is powered on, the FPGA is initialized first, and nSTATUS and CONF_DONE are set to low level. After nSTATUS is set to low level, it is reset. At this time, nCE of EPC2 is low level, so EPC2 is selected, so that the data flow is input from the DATA pin to the DATAO pin of the FPGA. After the configuration is completed, the FPGA sets CONF_DONE to high level, and EPC2 sets the DATA pin to high impedance state. Its FPGA configuration circuit is shown in Figure 2.

2.2 Key Circuit

Figure 3 shows a key circuit with 60 keys (i=1~60). Due to the complex external environment, the key lead is as long as 6 m. The protection diode VDi: turns on when the external interference signal is greater than VCC to protect the FPGA. The resistor Ri pulls up to limit the current. When the key is not closed, the FPGA input pin is always at a high level.

3 FPGA Internal Logic Design

The internal functions of FPGA are divided into scanning module, encoding module, control module and synchronous FIFO RAM module, as shown in Figure 4.

In Figure 4, K1~K60 are the input terminals of 60 keys, Scan is the working mode selection signal, Ready is the read ready signal, RdClk is the read clock signal, Data[7:0] is the data output, ModCtr is the encoding mode control signal, FIFOWEn is the FIFO RAM write enable signal, FIFOIn is the FIFO RAM data input, and State is the key status scan signal. Its working principle is: the scanning module periodically scans the key status, and its result is sent to the encoding module; the encoding module selects the encoding method according to the mode control signal ModCtr, and sends its result to the FIFO RAM; the control module generates a read control signal for the FIFO RAM; the MCU can read the key number and status data on the Data[7:0] data line through the Readv and RdClk control signals. [page]

3.1 Scanning Module

The scanning module mainly completes the scanning key state input and the key software de-jitter. The scanning key state input scans 60 input pins with a cycle of 5 m8 and stores the results in 60 two-bit state shift registers. The code is:

There are two ways to implement key debounce: hardware and software. In order to save costs and give full play to the functions of FPGA devices, this system design adopts software debounce. Figure 5 shows the software debounce process. In the figure, State is a 2-bit state shift register with an initial value of 0, and TimeDelay is a delay counter.

Software de-bounce process description: Perform an XOR operation on the 2-bit value of the state register, that is, m=State_1 Xor State_2. If m=1, it means that the button has an action, then set TimeDelay=1 to start the delay count; if m=0, it means that the button is in a de-bounce delay or stable state. At this time, judge TimeDelay. If TimeDelay=0, the button is in a stable state; if 0MaxDelay, it means that the button has been stable, and the result is sent to the encoder module. The key code for software de-bounce is as follows:

3.2 Encoding module

0 and 1 represent the on/off status of a key, and 60 keys require 8 bytes. In practice, the probability of a single key action is much greater than the probability of multiple keys acting simultaneously. If only the key information of the key that has changed its state is transmitted in 8-bit encoding, then only one byte is required for each key. Therefore, in order to reduce the burden on the MCU as much as possible and improve real-time performance, it is designed to transmit the corresponding key number and status data to the MCU only when the key changes its state. The encoding data format is shown in Figure 6.

The status bit is 1 bit, 0 means the button is closed, 1 means the button is open; the data is 6 bits, that is, 0X01~OX3C represents the 1st to 60th button respectively; 1 bit is an even parity bit. In this way, the button number and status can be transmitted once.

The encoder uses two working modes: continuous and random. The continuous working mode encodes all keys in sequence after each scan and obtains the current status of all keys; while the random working mode only encodes the keys whose status has changed after each scan.

3.3 Control module

The control module completes the functional control between MCU and FPGA, and has two functions: one is to select the working mode of the encoding module according to the Scan signal, and the other is to generate the reading operation timing of the FIFO RAM.

For mode control, the rising edge of Scan triggers the control module to make the encoding module enter the continuous working mode. After one scan is completed, the control module sends a control signal to make the encoding module enter the random working mode.

For reading data, the control module sets the Ready signal according to whether there is data in Data[7:0] of FIFO RAM. If there is data, Ready is low level; if there is no data, Ready is high level. RdClk is the read clock, which is equivalent to the confirmation signal. A pulse is sent after each data is read.

3.4 FIFORAM module

There are many types of interfaces for communicating with MCU, including serial port, I2C, parallel port, etc. In the application, the most suitable method can be selected according to the specific conditions such as MCU resources, project cost, and progress. This system design uses synchronous FIF0 RAM parallel port transmission. The FIF0 RAM module uses the standard module in the EDA software library.

4 Simulation Results

The Quartus II simulation tool provided by Altera is used, which integrates hardware test tools that are consistent with hardware real-time operation. The comprehensive simulation results are shown in Figure 7. The system clock SysClk is 12 kHz, and the simulation results show that the system design meets the requirements.

5 Conclusion

A special keyboard design scheme based on FPGA devices and described in VHDL language is proposed to solve the problem of long-distance, scattered, and multi-key action state recognition, which greatly saves PCB area and MCU I/O port resources. Parameters such as scan delay and scan interval in the module can be flexibly changed according to system requirements. FPGA devices make it easy to expand the circuit function and have extremely high stability and flexibility. This scheme has been applied in actual projects and has been verified on site to be stable and reliable.