At the 2019 Hot Chips Conference, Intel announced the latest details of its upcoming high-performance artificial intelligence (AI) accelerator, the Intel® Nervana™ Neural Network Processor, including the NNP-T for training and the NNP-I for inference. Intel engineers also introduced details of hybrid chip packaging technology, Intel® Optane™ data center-level persistent memory, and optical I/O chiplet technology.
“To realize the future vision of ‘AI everywhere’, we must address the data backlog, ensure that enterprises can effectively use data, process data where it is collected when necessary, and use upstream data and computing resources more wisely. Data centers and clouds need to provide high-performance and scalable general-purpose computing and specialized acceleration for complex AI applications. In the future vision of AI everywhere, a comprehensive solution is needed from hardware to software to applications.”
——Naveen Rao, Vice President and General Manager of the Artificial Intelligence Products Group at Intel Corporation
Transforming data into information and then into knowledge requires the coordination of hardware architecture and packaging, memory, storage, and interconnect technologies, which are constantly evolving and supporting emerging and increasingly complex application scenarios and AI technologies. AI-specific accelerators can provide customers with the right intelligence at the right time, such as the newly built Intel Nervana NNP.
Intel Nervana NNP-T – Built from the ground up to train deep learning models at scale. The Intel Nervana NNP-T (neural network processor) continues to push the boundaries of deep learning training. It prioritizes two key practical factors: training the network as fast as possible and completing the training within a given power budget. This deep learning training processor is built with flexibility in mind and balances compute, communication, and memory. While Intel® Xeon® Scalable processors have added AI instruction sets and provide a good foundation for artificial intelligence, the NNP-T is built from the ground up with the features and requirements needed to handle large models without having to provide the extras needed to support traditional technologies. To meet future deep learning needs, the Intel Nervana NNP-T is flexible and programmable so it can be customized to accelerate a variety of workloads, both existing and emerging.
Intel Nervana NNP-I – High-performance deep learning inference for major data center workloads. Designed for inference and to accelerate deep learning deployments at scale, the Intel Nervana NNP-I leverages Intel’s 10nm process technology and Ice Lake cores to deliver industry-leading performance per watt across all major data center workloads. In addition, the Intel Nervana NNP-I offers a high degree of programmability without compromising performance or power efficiency. As AI becomes ubiquitous in all workloads, having a dedicated inference accelerator that is easy to program, has low latency, allows for fast code porting, and supports all major deep learning frameworks will allow businesses to leverage the full potential of data into actionable insights.
Lakefield - a hybrid core in a three-dimensional package. Lakefield is the industry's first product to adopt 3D stacking and IA hybrid computing architecture, and will be used in a new class of mobile devices. Leveraging Intel's latest 10nm process and Foveros advanced packaging technology, Lakefield has significantly reduced standby power, core area, and package height compared to previous generations of technology. The top computing performance and ultra-low thermal design power brought by Lakefield allow new slim-appearance devices, two-in-one devices, and dual-screen devices to be always online and always connected with extremely low standby power consumption.
TeraPHY - In-Package Optical I/O Chiplets for High-Bandwidth, Low-Power Communications. Intel and Ayar Labs have demonstrated the industry’s first integration of Monolithic In-Package Optics (MIPO) with a high-performance System-on-Chip (SOC). Ayar Labs’ TeraPHY* optical I/O chiplet is co-packaged with an Intel Stratix 10 FPGA using Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology to deliver high-bandwidth, low-power data communications from the chip package over distances of up to 2 km for a limited period of time. This collaboration will remove inherent bottlenecks in performance, power, and cost in data transmission, helping to build computing systems for the next phase of Moore’s Law in a new way.
Intel Optane DC persistent memory – architecture and performance. Now shipping in volume, Intel Optane DC persistent memory is the first product in the memory/storage hierarchy to be called persistent memory and is a new layer in the hierarchy. Based on Intel® 3D XPoint™ technology, Optane DC persistent memory has a memory module form factor that delivers ultra-large capacity at near-memory speeds, nanosecond low latency, and localized persistent storage. Details of the two operating modes (Memory Mode and App Direct Mode) and performance examples show how this new layer enables a complete re-architecture of the data provisioning subsystem to support faster and new workloads.
Previous article:What are we still missing on the road to standardization of smart warehousing?
Next article:Application and analysis of isolation modules in intelligent buildings
Recommended ReadingLatest update time:2024-11-16 16:55
- Popular Resources
- Popular amplifiers
- More Hot Air (Tony Kordyban)
- Multi-port and shared memory architecture for high-performance ADAS SoCs
- Microcomputer Principles and Interface Technology 3rd Edition (Zhou Mingde, Zhang Xiaoxia, Lan Fangpeng)
- Microcomputer Principles and Interface Technology Examples and Exercises (Kong Qingyun, Qin Xiaohong)
- Huawei's Strategic Department Director Gai Gang: The cumulative installed base of open source Euler operating system exceeds 10 million sets
- Analysis of the application of several common contact parts in high-voltage connectors of new energy vehicles
- Wiring harness durability test and contact voltage drop test method
- Sn-doped CuO nanostructure-based ethanol gas sensor for real-time drunk driving detection in vehicles
- Design considerations for automotive battery wiring harness
- Do you know all the various motors commonly used in automotive electronics?
- What are the functions of the Internet of Vehicles? What are the uses and benefits of the Internet of Vehicles?
- Power Inverter - A critical safety system for electric vehicles
- Analysis of the information security mechanism of AUTOSAR, the automotive embedded software framework
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
- Innolux's intelligent steer-by-wire solution makes cars smarter and safer
- 8051 MCU - Parity Check
- How to efficiently balance the sensitivity of tactile sensing interfaces
- What should I do if the servo motor shakes? What causes the servo motor to shake quickly?
- 【Brushless Motor】Analysis of three-phase BLDC motor and sharing of two popular development boards
- Midea Industrial Technology's subsidiaries Clou Electronics and Hekang New Energy jointly appeared at the Munich Battery Energy Storage Exhibition and Solar Energy Exhibition
- Guoxin Sichen | Application of ferroelectric memory PB85RS2MC in power battery management, with a capacity of 2M
- Analysis of common faults of frequency converter
- In a head-on competition with Qualcomm, what kind of cockpit products has Intel come up with?
- Dalian Rongke's all-vanadium liquid flow battery energy storage equipment industrialization project has entered the sprint stage before production
- Allegro MicroSystems Introduces Advanced Magnetic and Inductive Position Sensing Solutions at Electronica 2024
- Car key in the left hand, liveness detection radar in the right hand, UWB is imperative for cars!
- After a decade of rapid development, domestic CIS has entered the market
- Aegis Dagger Battery + Thor EM-i Super Hybrid, Geely New Energy has thrown out two "king bombs"
- A brief discussion on functional safety - fault, error, and failure
- In the smart car 2.0 cycle, these core industry chains are facing major opportunities!
- The United States and Japan are developing new batteries. CATL faces challenges? How should China's new energy battery industry respond?
- Murata launches high-precision 6-axis inertial sensor for automobiles
- Ford patents pre-charge alarm to help save costs and respond to emergencies
- New real-time microcontroller system from Texas Instruments enables smarter processing in automotive and industrial applications
- Embedded USB driver-free device communication method based on WinUSB
- Generate random 0,1 signal
- Problems using Saber to simulate SPWM driving H-bridge via 2110
- Espressif ESP32-Korvo Audio Development Board Review Summary
- STM32mini MCU external clock method high-precision frequency capture
- TI DSP Bit Field and Register-File Struc...
- power supply
- [ESK32-360 Review] 3. LCD displays Chinese characters
- Analysis of the amplifier circuit of the photoelectric smoke detector
- Is there any teacher who can teach me how to learn microcontrollers?