SOPC Technology Design of Single-Chip DSP Processor Function System

Combining with the Nios II embedded soft-core processor 　　launched by Altera , a Nios II system SOPC solution with the functions of a conventional DSP processor is proposed; the characteristic of Nios II that it can customize fork instructions is utilized.

　　Complex multipliers, integer multipliers, floating-point multipliers and other hardware modules are designed and generated through Matlab and DSP Builder or directly with VHDL, and they are customized into corresponding instructions, thereby combining the flexibility of software with the high speed of hardware, and better solving the speed problems, non-reconfigurable hardware structure problems, long development and upgrade cycle and non-portability problems faced by traditional DSP processors.

　　With the development of microelectronics technology and computer tool software, the design concept and design method of programmable system on chip SOPC has become a trend. In order to solve the speed problems, non-reconfigurable hardware structure problems, long development and upgrade cycle and non-portability problems faced by traditional DSP processors, we applied the Nios II embedded soft-core processor launched by Altera and proposed a Nios II system SOPC solution with the functions of a conventional DSP processor.

　　Since the editable Nios II core contains many configurable interface module cores, users can use Quartus II and SOPC Builder to build Nios II and its peripheral systems according to design requirements. In addition, users can design various hardware modules for Nios II embedded processors through Matlab and DSP Builder, or directly use hardware description languages ​​such as VHDL, and add Nios II instruction system in the form of instructions, thus becoming an interface device of Nios II system and integrating with the entire embedded system on chip, instead of directly downloading to FPGA to generate a huge hardware system. It is these important features of Nios II that make the design of reconfigurable single-chip DSP processor functional system possible.

　　1 System Structure

　　This system is a single-chip DSP reconfigurable system that can realize various functions in digital signal processing. Among them, the establishment of the Nios II soft-core processor mainly plays a role in human-computer interaction and control. After receiving the control signal and data from the Nios II processor, the logic module of the FPGA realizes the corresponding hardware function. The system structure block diagram is shown in Figure 1. In addition to the soft-core processor Nios II, the memory and I/O interface as well as application modules such as FIR digital filter, IIR digital filter and DDS can be embedded in the FPGA as peripherals. In this way, the digital signal processing part of the entire DSP is fully integrated in the FPGA device, and each module is controlled by the Nios II processor. The Nios II processor system has an Avalon bus, which specifies the port connection between the controller and the slave module and the timing of the module-to-module communication. The digital frequency synthesizer DDS is connected to the Nios II processor through the Avalon bus, which can easily complete the control and data transmission.

　　The FPGA of this system uses Cyclone EPICl2, which has 12 060 logic units (LE) and 2 phase-locked loops (PLLs), provides 6 outputs and hierarchical clock structure and complex clock management circuit design. The ultra-high-speed 10-bit D/A converter 565l is selected to realize the D/A conversion function, and the maximum conversion rate is 150 MHz. Under the control of the Nios II processor, the entire system can realize FIR digital filtering, IIR digital filtering, fast Fourier transform (FFT) algorithm, encoding/decoding, DDS functional module design, and the signal generator composed of it with functions such as digital control frequency modulation, orthogonal carrier modulation and demodulation, and digital control phase modulation.

　　The selection of each functional module in the system, as well as the output signal modulation mode and frequency, can be freely selected through external buttons. Next, a Nios II system with conventional DSP processor functions is constructed.

　　2 Nios II Embedded System Design Process

The Nios II embedded processor is a CPU soft core specially optimized 　　for single-chip programmable system ( SOPC ) design launched by Altera.

It is a general-purpose RISC (reduced instruction set) embedded CPU that can be flexibly customized by users. It uses the Avalon bus structure communication interface, with enhanced memory, debugging and software functions, and can use assembly or C, C++ and other languages ​​for program optimization and development; it has a 32-bit instruction set, 32-bit data channel and configurable instruction and data buffers. Different from the characteristics of ordinary embedded CPU systems, its peripherals can be flexibly selected or added or deleted, and user logic can be customized as peripherals, allowing users to customize their own instruction sets. Customized instructions composed of hardware modules can complete complex software processing tasks through hardware algorithm operations, and can also access memory or interface logic outside the Nios II system. Designers can use Nios II plus external Flash, SRAM, etc. to build an embedded processor system on FPGA.

　　A complete SOPC system based on Nios II is a complex system of hardware and software, so it can be divided into hardware and software during design. The hardware design of Nios II is to customize the appropriate CPU and peripherals, which is completed in SOPC Buider and Quartus II. Here, many features and even instructions of NiosII CPU can be flexibly customized; a large number of IP cores provided by Altera can be used to speed up the development of Ntos II peripherals and improve peripheral performance; third-party IP cores or VHDL can also be used to customize peripherals. After completing the hardware development of Nios II, SOPC Buider can automatically generate a software development kit SDK corresponding to the customized Nios II CPU and peripheral system, memory, peripheral address mapping, etc.; based on the generated SDK, enter the software development process. Assembly or C language, or even C++ language can be used for embedded program design, and GNU tools or other third-party tools can be used to compile, link and debug programs.

　　3 System Hardware Design

　　The hardware system of the system consists of three parts: FPGA part, memory part and peripheral components part. The FPGA part is built in the FPGA, and it is this part that needs to be designed in SOPC Builder. It includes a NiosII CPU core, an internal clock, an Avalon bus controller, a JTAG_UART communication module for connecting the download and debugging program of the Nios II core, a DDS interface module and a DDS module, a FIR, IIR digital filter interface module and a functional module, a codec module and an interface module, and a Flash memory module. Its design is different from general embedded development. The corresponding peripheral module core can be added outside the Nios II core (but still in the same FPGA chip), and connected to the Nios II through the on-chip Avalon bus. In order to make the Nios II system with DSP processor function work normally, some control keys are connected to the periphery of the FPGA to schedule the application of each module.

　　3.1 Building a Nios II Embedded Processor System

　　First, use Quartus II to create a project, and select the target device as Cyclone EPIC12;

Then use SOPC Bider to create Nios II component model, generate hardware description file, lock pins, perform synthesis and adaptation, generate Nios II hardware system download file; then build Nios II embedded system, add required components (such as Nios II CPU core, timer Timer, JTAG_UART, Avalon tri-state bus bridge, key input I/O port and Flash, etc.) from SOPC Bider component column. In addition, in order to realize Nios II processor read and write access to EPCS Flash memory, an EPCS Serial F1ash Controller component is also added. Through this controller, SOF file used for FPGA configuration and software running by CPU are stored in EPCS device together, so as to greatly simplify the hardware system composition structure. In order to ensure that the address arrangement of all components is legal, the address of each component should be automatically allocated; finally, full compilation (i.e. analysis, synthesis, adaptation and output file assembly) is performed to complete the design of Nios II hardware system.

　　After the Nios II hardware system design is completed, the configuration file is downloaded to the specified FPGA. Through the SOPC Builder software window, you can enter the Nios II IDE software development environment for software design.

　　3.2 Establishment of DSP processor functional system

　　Using DSP Bider to design DSP modules on FPGA can achieve high-speed DSP processing. However, in practical applications, in addition to requiring high DSP speed, the algorithms processed by DSP are often complex. If DSP Bider is used alone to implement pure hardware DSP modules, it will consume too many hardware resources, so sometimes it is impossible to complete many models with complex algorithms. Nios II is an embedded microprocessor soft core built on FPGA, and one of its important features is that it has custom instructions.

　　In DSP algorithms, some operations (such as complex multipliers, integer multipliers, floating-point multipliers, etc.) will appear repeatedly, but there are no relevant instructions specifically used for complex multiplication and floating-point multiplication in general-purpose CPUs. In system design, use MATLAB, DSP  Buider or VHDL to design and generate hardware modules such as complex multipliers, integer multipliers, floating-point multipliers, etc. After making some corrections to the above files in the Quartus II environment, customize them to corresponding instructions in the SOPC Buider window, and set or modify the clock cycle for executing the instruction. When performing DSP algorithm operations, these custom instructions can be used for embedded programming through assembly or C language, or even C++ language.

　　According to the algorithm of complex number operation, assuming there are two complex numbers a+bj and c+dj, the multiplication can be expressed as:

　　Figure 2 is a complex multiplier model designed using MATLAB and DSP Builder. It implements a 16-bit complex multiplication, where both the imaginary and real parts are 16 bits, and a 32-bit value can be used to represent the complex number. In the design, NiosII is 32-bit data, which can hold exactly two complex numbers.

　　To set up this complex multiplier hardware module to the corresponding instructions, you must also do the following:

　　① Click the SignalCompiler icon to convert it, select the device (use Cyclone) and Quartus II synthesizer. After conversion, it will generate the PTF file of SOPCBuider.

　　② After exiting MATLAB, modify the top-level VHDL file of the complex multiplier generated after conversion in the Quartus II environment. Double-click the CPU item in the SOPC Builder window to enter the "Instruction Addition" editing window and set this hardware module to a custom complex multiplication instruction.

　　After the instruction is generated, you can use Quartus II to edit the C program for testing; after the test is successful, you can use the complex multiplication instruction when you encounter complex multiplication in the DSP algorithm calculation. This method generates instructions from commonly used hardware modules and implements more complex DSP algorithms in FPGA through a design method that coexists software and hardware. It can combine the flexibility of software and the high speed of hardware, and better solve many problems in modern DSP design. However, for the DDS module, it is still solidified in the FPGA in the form of hardware. Amplitude, phase and frequency modulators can be designed using DDS as needed.

　　In addition, the peripherals of Nios II can be customized arbitrarily. All the peripherals of Nios II system are connected to Nios II CPU through Avalon bus. Avalon bus is an on-chip bus with relatively simple protocol. Nios II exchanges data with the outside world through Avalon bus. In this system, the AvalonSlave peripheral method is adopted to add the customized AvalorL bus component A/D conversion interface module and D/A interface module to control the sampling A/D work and the waveform data output of high-speed D/A; while the customized Avalon bus component DDS module interface and DSP function conversion control interface are used for Nios II CPU to control the DDS module and to control the selection of DSP function through external keyboard.

　　Conclusion

　　The entire system is in a single FPGA programming chip except for the A/D, D/A converter and the control selection keyboard. Because NiosII is used as the CPU, it is possible to customize instructions and various interface module components through the Avalon bus, making the entire DSP system flexible and diverse, and it has more and more applications in modern DSP technology.