Design of high-precision time-to-digital conversion circuit based on FPGA

Abstract: This paper introduces a design method for high-precision time-to-digital conversion circuit based on FPGA. By using the on-chip phase-locked loop (PLL) and circular shift register, a high time resolution can be obtained with a low system clock and less logic resources are occupied. It can be used as an independent functional circuit or as an IP core to be easily transplanted to other systems on chip (SOC). When implemented on Altera's Stratix and Cyclone series chips, the time resolution can reach up to 3.3ns. Timing simulation and hardware testing show the feasibility and accuracy of this method.

1. Introduction

Time to Digital Converter (TDC) is widely used in research fields such as particle lifetime detection, automatic detection equipment, laser detection, medical image scanning, phase measurement, and frequency measurement in high-energy physics [1]. For example, TDC devices are widely used in medical image scanners PET. The principle is to detect a pair of gamma-ray photons generated after the disappearance of the positron pair in the human body. The released gamma-ray photons are compared with the threshold using an analog circuit, and a trigger pulse is generated when it is higher than the threshold. The digital TDC circuit measures the arrival time of the trigger pulse. The resolution of TDC in early devices of this type was 2.5ns, and the resolution of new devices has reached 1.4ns [2]. In laser detection, TDC circuits are used to measure TOF (Time of Flight for Laser), that is, to distinguish the time from the laser source to the target and then back to the laser detector [3]. In addition, TDC is also one of the means to indirectly implement ADC. If an ATC (Analog to Time Conversion) is added before the analog signal, the ADC process can be completed with the subsequent TDC part.

Early TDC circuits were usually composed of discrete components on a printed circuit board (PCB), and were usually analog-digital hybrid circuits, so the power consumption and volume were large, and the circuit consistency was poor. The advancement of very large scale integrated circuit (VLSI) technology has enabled TDC design to develop in the direction of high integration, low cost, and low power consumption while maintaining high resolution. At the same time, all-digital integrated circuit design has always been the goal pursued by circuit designers due to its simple process, low design cost, low design difficulty, and high tape-out success rate. All-digital TDC is also a concern for researchers.

Reference [4] reported a fully digital TDC design based on a ring delay gate in 1993. The design achieved 13-bit digital conversion output using a 1.5-micron CMOS process, with a chip area of ​​1.1 mm2 and a resolution of 0.5 ns. Later in 2003, the author reported a fully digital analog-to-digital conversion circuit in reference [5], which was based on a fully digital TDC implementation using a ring delay gate. The reference stated that an 18-bit fully digital ADC was achieved in an area of ​​0.45 mm2 using a 0.8-micron CMOS process.

With the continuous improvement of integrated circuit (IC) manufacturing technology, the programmable logic device (PLD) industry represented by FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device) has developed rapidly, gradually eroding the market share of application-specific integrated circuit (ASIC). This development makes TDC design based on PLD possible. As we all know, the design based on PLD can effectively shorten the development cycle.

Improve design flexibility and reliability, reduce design costs and eliminate tape-out risks. The successfully designed IP core (Intellectual Property Core) is relatively independent of the process and can be flexibly transplanted to other SOCs, making design reuse very convenient.

This paper proposes a design method for high-precision TDC based on FPGA by referring to the circular delay gate method in references [4] and [5]. In order to adapt to FPGA design, the delay gate method is modified. If the delay gate design is simply transplanted, it will not work in FPGA. Because it is different from ASIC design, the gate circuit in FPGA is realized by EDA software synthesis. First, it is difficult to ensure the consistency of delay between gates; second, it is difficult to ensure the coordination with other circuits in terms of timing. In order to improve the resolution, unlike the simple counting type TDC, this design also uses the coarse counting and fine counting circuits similar to the circular delay gate design to measure the given time quantity. The coarse counting part controls the measurement range, and the fine counting part is realized by the circular shift register instead of the circular delay gate. This conversion circuit is implemented on the Altera series chip using QuartusII 4.2 as the software platform. The timing simulation shows that the maximum resolution can reach 3.3ns.

2. Basic working principle

The principle block diagram of the TDC system based on the ring delay gate is shown in Figure 1. PA is the starting pulse, and the specific structure delay chain composed of NOT gates provides the delay information of the pulse PA. At the rising edge of PB, the delay information is latched and encoded by the latch encoding circuit and then output. The time difference between the pulse PB and PA is represented by the digital quantity of the encoded output. The experimental results show that this method is suitable for ASIC implementation, but not for FPGA implementation. The reason is that the synthesis results of the synthesizer in the current EDA tool are based on the logical function of the design object, but do not pay attention to the specific circuit structure of the designer. According to the internal circuit characteristics of the FPGA circuit, the delay chain structure provided by the reference [2] is not suitable for implementation on FGPA. The uncertainty of the internal wiring delay of the FPGA will greatly increase the discreteness of the delay information of each unit. Reference [6] introduces the CPLD implementation of this method, but this method adds many constraints for specific chips. Each NOT gate in the delay chain is implemented by a logic macro unit LE on the chip. Due to the relatively small capacity of CPLD, the chip resource rate is low and the portability between chips is poor. In addition, due to the difference in the structure of FPGA and CPLD, it cannot be implemented on FPGA for the time being. The following introduces a new FPGA-based high-precision TDC design method.

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The principle of the FPGA-based TDC circuit is shown in Figure 2. The circuit includes a 16-bit ring shift register, an encoder circuit with 16-bit input and 4-bit output, a clock management module, an 8-bit universal counter unit, a reset logic, and an output logic part. The ring shift register and the encoder constitute the fine counter part of the circuit, which is used to control the circuit measurement accuracy; the universal counter is the coarse counting part, which determines the time measurement range of the circuit; the clock management module uses the internal PLL resources of the FPGA to provide a suitable working clock for the shift register; the reset logic controls the reset action of the entire TDC circuit; and the output logic combines the fine counting and coarse counting parts of the converted digital quantity into the final system output.

The 16-bit shift register is shown in Figure 3. It consists of 16 D flip-flops with asynchronous reset and set terminals. In the initial state or after reset, the circuit node p15 is set to a high level, and other nodes (p14 to p0) are reset to a low level. During normal operation, the high level appears cyclically in the 16 circuit nodes at the rising edge of the shift pulse clk. By checking the state of the circuit node at a certain moment (the position of the high level), the number of shift pulses clk experienced by the system can be determined. The time resolution of the circuit is the clock cycle of clk. The encoder encodes the state of the shift register node and serves as the 4-bit output of the fine counting part of the measurement circuit. The general counter works on the rising edge of the shift register node p15. Its counting cycle is 16 times the shift pulse cycle. It completes the carry count from low to high and serves as the 8-bit output of the coarse counting part of the measurement circuit. The reset logic is responsible for the reset operation of the circular shift register and the general counter. The output logic combines the 8-bit and 4-bit data of the coarse counting and fine counting outputs into the final output of the measurement circuit, and completes the data verification.

The single-counter pulse width measurement circuit based on FPGA uses the method of counting within the time corresponding to the pulse width. Because the counter may skip codes or miss codes when working at high frequencies, resulting in system error output, it is difficult to improve the resolution [7]. Compared with the single-counter pulse width measurement circuit, the use of a simple fine counting circuit can greatly improve the circuit's time resolution and avoid the code skipping phenomenon at the limit operating frequency of the general counter. The fine counting circuit also occupies very few on-chip resources.

3 System Implementation and Optimization

The Stratix and Cyclone series FPGA chips provided by Altera have an embedded phase-locked loop (PLL) module, which can multiply and divide the external clock and perform phase shift operations, program the duty cycle and external clock output, and perform system-level clock management and offset control. It is often used to synchronize the internal device clock and the external clock, so that the internal clock frequency is higher than the external clock, the clock delay and clock offset are minimized, and the clock to output (TCO) and setup (TSU) time are reduced or adjusted, thereby providing a complete clock management solution. Using Altera Quartus? II software, you can call the PLL inside the chip to implement the corresponding function without any external devices.

The system clock management module calls the internal PLL of the FPGA to implement it, and the parameters are set through QuartusII: Ratio is the multiplication/division factor (Ratio) is 4, the output clock phase shift (Ph) is 0, and the output clock duty cycle (DC) is 50%.

The time resolution of the TDC circuit depends on the fine counting part composed of the circular shift register and the encoding circuit. To obtain the correct measurement data, it is necessary to ensure the correct encoding of the output state of the shift register. Unlike ASIC design, it is difficult for designers to predict the situation after EDA software layout and routing. Moreover, the layout and routing results of programmable devices with different structures and performances are also different. In addition, the clock-to-output time (TCO) of the D flip-flop that constitutes the shift register and the time (TSU) for the D flip-flop input to be stably established on the metal connection line also have certain discreteness, which makes the shift register under high-frequency shift pulse (nanosecond level) work. Glitches occur during state transition, affecting the correct output of the encoding. At the same time, the inherent delay characteristics of the encoder also limit the time resolution of the system. The pulse width measurement circuit system adopts an optimized encoding algorithm, so that the encoding output under high-frequency shift state can accurately reflect the state of each node on the circular shift register, thereby ensuring the measurement accuracy of the system; when the shift clock is 333MHz (cycle 3ns), the encoder can work normally on Altera's Stratix and Cyclone series chips.

The system consists of two circuits: coarse counting and fine counting. The coarse counting circuit works on the rising edge of the high-bit output of the fine digital circuit (p15 in Figure 3). However, due to the delay of the coarse counting circuit, the output data may be misread at the rising edge of the measured pulse (clks).

In order to solve the misreading phenomenon, an error correction circuit is added to the output logic module. After the measured pulse clks is delayed by clk period, a new clock clks1 is generated. At the rising edge of clks and clks1, q1 and q0 are sampled at the same time and the sampled data is processed and output as the final data, thus effectively solving the misreading phenomenon.

The shift pulse operating frequency is the time resolution of the measurement circuit. Through the clock management unit, a low external clock can be used to obtain high measurement accuracy.

3 Simulation results and test data

In order to test the time resolution of the system, a specific functional circuit is added to the basic time-to-digital conversion circuit to enable it to have the function of continuously measuring the clock pulse width. The test object is the high level duration of clks. By changing the frequency of the clock pulse source to record the corresponding measurement data of the circuit, the time resolution of the TDC circuit can be obtained.

This paper uses QuartusII Web Edition 4.2 as the software platform. Experiments show that the timing simulation of this TDC design on all mainstream Altera chips can pass smoothly. The timing simulation adapted to the Cyclone EP1C3Q240C8 chip shows that the shift clock is 333M (that is, the resolution is 3ns), and the obtained test data output correctly reflects the width of the measured pulse. The delay from the falling edge of the measured pulse to the establishment of the measured data is 5ns. [page]

The pulse width measurement circuit composed of this TDC is implemented in the Cyclone EP1C3Q240C8 chip. The system external clock is 25Mhz, the PLL is set to a multiplication factor of 8, and the SP1641B signal generator provides a fixed measured pulse frequency F. The distribution of the time resolution Res is shown in Figure 4. The test data shows that Res is between 4.9-5.1ns, and the theoretical value is 5ns.

Measurement and simulation data show that the circuit can achieve nanosecond time resolution, occupy less logic resources, and can be used as a dedicated measurement circuit on a low-density chip, or embedded as a functional module in a specific function system-on-chip (SOC) on a high-density chip; the conversion speed of the TDC circuit is also in the nanosecond level, making the circuit suitable for real-time data acquisition and high-speed data processing systems. Adjustable accuracy is also a major feature of this design. The operating frequency of the shift pulse determines the conversion accuracy of the conversion system. The clock management unit can generate shift clocks of different frequencies, so that the measurement accuracy can be appropriately adjusted according to specific needs.

3 Conclusion

This FPGA-based time-to-digital conversion circuit design achieves high measurement accuracy while occupying less chip resources, and the data conversion speed is also in the nanosecond level during operation; the circuit interface of this design is simple and can be used as an independent functional circuit, or it can be easily embedded in other systems as a functional module IP core [8] to realize specific functions. Timing simulation and hardware testing based on Altera chips show the feasibility and accuracy of this method.