Research on Direct Sequence Spread Spectrum and Its Implementation on FPGA

Spread spectrum communication is a unique communication method in modern communication systems. It has many advantages such as strong anti-interference and anti-multipath performance, high spectrum utilization, and multiple access communication. Direct sequence spread spectrum is adopted by many existing and future cellular communication systems, and is widely used in military communication networks and systems.
With the development of microelectronics manufacturing technology, programmable logic devices have made great progress. Field programmable logic devices (FPGAs) that can complete ultra-large-scale complex combinational logic and sequential logic are increasingly widely used in the design of electronic systems.
Using Quartus II software as a development tool, a baseband direct sequence spread spectrum communication system is implemented using FPGA, which includes a transmitting module and a receiving module.

1 Basic principles of direct sequence spread spectrum communication system
Direct sequence spread spectrum system (DS-SS), referred to as direct spread system, uses the information signal to be transmitted to multiply with a high-speed pseudo-random code waveform to modulate a certain parameter of the radio frequency signal to expand the bandwidth of the transmission signal. The principle is shown in Figure 1.

At the transmitter end, the composite code formed by multiplying the data signal to be transmitted with the pseudo-random code waveform modulates the carrier and then transmits it by the antenna. At the receiver end, a local reference pseudo-random code synchronized with the pseudo-random code in the transmitter is generated to despread the received signal. The despread signal is sent to the demodulator for demodulation to recover the transmitted information.

2 Design and implementation of the transmission module of the direct sequence spread spectrum communication system
The transmission subsystem mainly includes the information code input module, the spread spectrum pseudo-random code generation module and the spread spectrum module.
2.1 Information code input module
This module provides the input data source for system simulation and debugging, and the data is solidified in the ROM. It is set to 200 words long and 1 bit wide. Design the address control module of the ROM, drive a counter with a given clock to cyclically generate address information, so that the information to be transmitted stored in the ROM is continuously output.
Use Verilog language to design the address control module, use the LPM custom ROM module provided by QuartusⅡ, and use the schematic design to generate the top-level entity, and you can get the circuit shown in Figure 2 and the simulation result shown in Figure 3.

From the results, we can see that under the control of the clock, the address input terminal generates address information cyclically to output the data in the ROM cyclically.
2.2 Digital design of PN code generator
The PN code generator of the system adopts an m-sequence generator. In this design, the m-sequence generator uses a 6-stage shift register, that is, n=6, and its corresponding characteristic polynomial is f(x)=x6+x+1. Feedback is introduced from the 1st and 6th stages. The structure of the sequence generator is shown in Figure 4.

The 6-level m-sequence generator can generate a PN code sequence with a period of 63, because if the register starting sequence is all zero, the output sequence will also be all zero. This will cause the PN code generator to enter a deadlock state. Therefore, in order for the PN code generator to work properly and generate the expected PN sequence, it must be ensured that at least one of the registers is 1 at the beginning. The initial state of the PN code register at the design transmitter is "111111". The PN code
generator can be implemented using a VHDL program. The structured description method can also be used. The register transfer description method can be used. The simulation results of the two methods are the same. The design uses the register transfer description method to facilitate the modification of the initial state of the register in the design. The simulation results are shown in Figure 5.

2.3 Implementation of spread spectrum modulation
In practical applications, in order to achieve the purpose of data symbol spread spectrum, the usual practice is to multiply the signal to be transmitted with a spread spectrum code sequence, and the spread spectrum sequence has a much narrower time width than the data bit, so that the spread spectrum sequence has a much higher frequency band than the data sequence.
2.4 Comprehensive simulation of the transmission subsystem
Combined with the previous modules, the entire transmission subsystem will take out the information stored in the ROM and perform modulo-2 addition with the pseudo code sequence from the PN code generator to complete the spectrum expansion of the signal. The system circuit diagram and simulation results are shown in Figures 6 and 7 respectively. In the simulation results, clk is the global clock, clk4 is the reading clock, clk204 is the PN code generator clock, data is the input data, and kuopinout is the spread spectrum output data. It can be seen from the results that the function of spread spectrum modulation is realized.

It can be seen from the simulation waveform that the designed transmitter completes the m-sequence generation and spread spectrum modulation functions as required.
3 Design and implementation of the receiving module
Compared with the transmitting subsystem, the receiving subsystem is a complex digital signal processing process, which mainly completes the synchronous capture and despreading of the digital baseband signal.
3.1 Design of the local PN code generator
The local PN code generator has the same structure as the PN code generator in the transmitting subsystem. The m-sequence generator is also used, which will not be described here.
3.2 FPGA design and implementation of the synchronous capture module
The key technology for despreading the spread spectrum communication system is the synchronization of the spread spectrum signal. The performance of the spread spectrum signal directly affects the performance and reliability of the system, and the key to synchronization lies in the PN code capture method.
The synchronous capture of the spread spectrum code is to solve practical problems in engineering, which includes two aspects: simple synchronous capture equipment and short synchronous capture time. Although simple equipment is an indicator pursued by any system, this indicator is more important in the spread spectrum communication system. How to shorten the synchronous capture time of the spread spectrum code without increasing or reducing the amount of equipment is the main research content of the synchronous capture of the spread spectrum code.
The synchronous capture of spread spectrum codes generally has the following steps: (1) Determine the area of ​​the spread spectrum code phase to be searched. (2) Adjust the phase of the local reference spread spectrum code. (3) Solve the correlation function value of the spread spectrum code. (4) Make a decision on the correlation value.
Based on comprehensive consideration of the above factors, the capture circuit of the digital baseband matched filter is designed. The biggest advantage of matched filter capture is that the capture time is short, and the despreading and demodulation of the spread spectrum signal can be completed quickly. Under ideal conditions, the digital matched filter (DMF) capture system only needs one spread spectrum sequence cycle at most to detect the synchronization phase and realize the capture of the spread spectrum sequence.
In the matched filter, the PN code sequence is correlated with the channel data to be despread, and the sum of the correlation operations is calculated. Since the important characteristic of the PN code is that its autocorrelation coefficient is high and the mutual correlation coefficient is low, as long as the PN codes of the two related signals are consistent, the peak value of the correlation integral can be obtained. This means that the despreading is successful. The matched filter used for PN code synchronous capture generally adopts a delay line matched filter. During the capture process, the received signal is continuously correlated with the local pseudo code sequence. The correlation result at any time is compared with a threshold. If the threshold is exceeded, it means that the phase of the local PN code sequence is synchronized with the phase of the received code sequence at this moment. The synchronization process is completed, and the despreading of the spread spectrum signal is also completed. Due to the autocorrelation characteristics of the PN code, there will always be a correlation peak in one code period. In only T=NTC time, all possible phases of the sequence are searched once, with a high phase search speed, so its capture time is very short. However, when the spread spectrum code period is long, the conventional method requires a FIR filter with more taps. Such a filter is difficult to implement and occupies more resources. Its hardware complexity will increase exponentially with the length of the spread spectrum code. Therefore, it is key to implement the matched filter in FPGA in a simple and effective way.
Based on the above ideas, the digital matched filter implemented by FPGA consists of two groups of delay shift registers, multipliers, arithmetic accumulators and a group of coefficient registers. The structural diagram is shown in Figure 8.

In Figure 8, the sequence shift register is mainly used to store the input spread spectrum data collected by the high-speed clock, and after passing through the fixed delay unit, the data is sent to the multiplier for correlation operation with the pre-stored PN code. The shift register group constitutes a matched filter array, the purpose of which is to complete the matching of the spread spectrum signal with the local pseudo code.
The simulation results of the digital baseband matched filter are shown in Figure 9.

3.3 FPGA implementation of despreading module
For direct spread system, only after the synchronization of spread spectrum sequence is completed, can the received spread spectrum signal be despread with the synchronized PN code sequence. For baseband signal, the despreading method is the same as spread spectrum. The usual practice is to multiply the received spread spectrum signal with the locally synchronized PN code sequence to restore the spread spectrum broadband signal to a narrowband signal to demodulate the transmitted information data.
3.4 Comprehensive simulation of baseband system
Combine the above modules to perform comprehensive baseband function simulation, the simulation diagrams are shown in Figures 10 and 11.

In the transmitting subsystem, the transmitting PN code generator is a 63-bit sequence, which is used to spread the information code. In the receiving subsystem, the local PN code generator is also a 63-bit sequence, and the frequency and codeword are the same as those of the transmitting end, but the phase is different. Synchronous capture uses the matched filter method to correlate and match the local PN code with the PN code in the received signal. After synchronous capture is achieved, the local PN code is started for synchronous phase shift and sent to the despreading module for despreading.
The system simulation results are shown in Figure 11.

It can be seen from the results that the system can achieve the correct despreading function when the PN code is captured.

4 Conclusion
The basic principle of direct sequence spread spectrum is studied, and a direct sequence spread spectrum system based on FPGA is designed and implemented. The design circuit and simulation results of the system are given, and the correctness and feasibility of the design are verified by the results.