Design and Simulation Analysis of ARM Parallel Bus Based on FPGA

　　In the design of digital systems, the FPGA+ARM system architecture has been used more and more widely. FPGA mainly realizes high-speed data processing; ARM mainly realizes system process control, human-computer interaction, external communication and FPGA control and other functions. Serial bus interfaces such as I2C and SPI can only realize low-speed communication between FPGA and ARM; when the amount of data to be transmitted is large and high-speed transmission is required, a parallel bus is needed to carry out high-speed data transmission between the two.

　　Based on the ARM processor LPC2478 and the FPGA device EP2C20Q240, the following takes the read operation timing of the ARM external bus as an example to study the high-speed transmission parallel bus between the two. Among them, the data bus is 32 bits; and a 1024x32bits SRAM high-speed storage buffer is constructed inside the FPGA to facilitate the ARM processor to quickly read and write data inside the FPGA.

　　1 Working principle of ARM parallel bus

　　The external parallel bus of the ARM processor LPC2478 consists of 24 address buses, 32 data buses and several control signal lines such as read, write, and chip select. According to system requirements, the data bus width can also be configured to several working modes such as 8 bits, 16 bits, and 32 bits.

　　In this design, the signals of ARM external bus are: CS.WE.OE.DATA［310］.ADDR［230］.BLS, etc. CS is chip select signal, WE is write enable signal, OE is read enable signal, DATA is data bus, ADDR is address bus, BLS is byte group select signal. The timing diagram of ARM external bus read operation is shown in Figure 1.

　　According to the timing of the ARM external parallel bus operation, the read and write operations of the ARM external bus are all performed when CS is valid at a low level. Since the read and write operations cannot be performed at the same time, the WE and OE signals cannot be low at the same time.

　　The data bus DATA is a bidirectional bus, which requires FPGA to realize bidirectional data transmission. The constraint relationship between the timings is given in the timing diagram. When designing FPGA, the setup time and hold time requirements of the ARM signal should be met, otherwise unstable reading and writing may occur.

　　2 FPGA Parallel Bus Design

　　2.1 FPGA port design

　　The block diagram of the external parallel bus connection between FPGA and ARM is shown in Figure 2. Since the SRAM storage unit inside the FPGA is 32 bits, there is no need to select a byte group, so the BLS signal can be disconnected. In order to facilitate the rapid transmission of data between ARM and FPGA, the SRAM inside the FPGA must perform read and write processing with the ARM processor and exchange data with other logic modules inside the FPGA, so the SRAM is implemented using a dual-port RAM.

　　From the perspective of the port's direction characteristics, the DATA port is INOUT (bidirectional) mode, and the other ports are IN (input) mode. From the perspective of the port's function, clk20m is a global clock. When implementing it, the FPGA's global clock network should be used. This can effectively reduce clock delays and ensure the correctness of the FPGA's timing. ADDR is a 16-bit address bus that is input from the ARM device to the FPGA. DATA is a 32-bit bidirectional data bus. The design of the bidirectional bus is the focus of the entire design. OE is the read enable signal that the ARM inputs to the FPGA. [page]

　　WE is the write enable signal input from ARM to FPGA. CS is the chip select signal input from ARM to FPGA. When FPGA is not selected by ARM, it must output high impedance to avoid bus conflict.

　　2.2 FPGA Bidirectional Bus Design

　　In the parallel bus design of FPGA, if both the top-level and bottom-level modules use bidirectional IO ports, the design principles must be followed; otherwise, it is not conducive to the synthesis of VHDL programs. The design principle of bidirectional IO ports is: only the top-level design can use INOUT type ports, and in the bottom-level modules, the top-level INOUT ports should be converted into independent IN (input) and OUT (output) ports and add direction control ports. The VHDL code of the top-level design is as follows:

　　Among them, DATA_i, DATA_o and output_en are all signals inside the FPGA. In each level of internal modules, these three signals can be used to perform unidirectional IO control. In this way, the bidirectional DATA port in the top-level design is converted into the internal unidirectional DATA_i (input), DATA_o (output) and output_en (output enable). In each internal module, the combination of these three signals and ADDR, OE, WE, CS and other signals can easily realize the function of the ARM bus interface. The key VHDL code implemented is as follows:

　　3 Simulation Results Analysis

　　The FPGA parallel bus is simulated by QuartusII simulation tool; the simulation results are shown in Figure 3. According to the read and write timing diagram requirements of the ARM parallel bus, it can be seen from the simulation results that the FPGA bus interface design meets the design requirements. Since the selected FPGA device has a logic analyzer function module inside, the FPGA design module is tested online by using the SignalTapII logic analysis tool in the QuartusII software. It is found that the bus timing meets the requirements of the ARM parallel bus and works stably, which verifies the correctness of the design and simulation results from another perspective.

　　4 Conclusion

　　As FPGA and ARM technologies are increasingly widely used, the need for fast data transmission can be easily met by designing a parallel bus interface to achieve data exchange between the two. Therefore, it is particularly important to design an FPGA parallel bus that meets the system requirements. The ARM external parallel bus interface of the FPGA designed in this paper meets the timing requirements of the bus and has been applied in a certain aviation airborne radar transponder. The system runs stably and has good performance. The above design and simulation methods also have a certain reference role for other similar designs.