Design of equal-precision frequency measurement based on STM32 and CPLD

In electronic engineering, resource exploration, instrumentation and other related applications, frequency measurement is one of the most basic and common measurements in electronic measurement technology, and frequency meter is also an indispensable measurement tool for engineering technicians. However, traditional frequency measurement methods have great limitations in practical applications. The measurement accuracy of frequency meters based on traditional frequency measurement principles will change with the change of the frequency of the measured signal. The measurement accuracy of the traditional direct frequency measurement method will decrease with the decrease of the measured signal frequency, and the measurement accuracy of the period measurement method will decrease with the increase of the measured signal frequency. This paper proposes a design of a wide-band digital frequency meter based on ARM and CPLD, using the microcontroller STM32 as the core control chip and the CPLD programmable logic device to achieve equal-precision frequency measurement of gate measurement technology.

Technical indicators of this design:

Frequency measurement range: 1Hz~200MHz, resolution is 0.1Hz, relative error of frequency measurement is one millionth.
Period measurement: signal measurement range and accuracy requirements are the same as those of frequency measurement function.
Duty cycle measurement: accuracy is 99%.
Counting range: 0~1000000000, can be manually paused and reset.
Power consumption: 5V×250mA=1.25W.

Principle of equal-precision frequency measurement

Common direct frequency measurement methods mainly include frequency measurement method and period measurement method. The frequency measurement method is to record the number of change cycles (or pulses) Nx of the measured signal within a certain gate time Tw, then the frequency of the measured signal is: fx=Nx/Tw. The period measurement method requires the frequency fs of the standard signal. Within a period Tx of the measured signal, the number of periods Ns of the standard frequency is recorded, then the frequency of the measured signal is: fx=fs/Ns. The count values ​​of these two methods will produce ±1 word error, and the test accuracy is related to the value Nx or Ns recorded in the counter. In order to ensure the test accuracy, the period measurement method is generally used for low-frequency signals, and the frequency measurement method is used for high-frequency signals. However, due to the inconvenience of testing, the equal-precision frequency measurement method is proposed. The equal-precision frequency measurement method is developed on the basis of the direct frequency measurement method. Its gate time is not a fixed value, but an integer multiple of the period of the measured signal, that is, it is synchronized with the measured signal. The control timing diagram of the equal-precision frequency measurement system is shown in Figure 1.

Figure 1 Control timing diagram of equal-precision frequency measurement system

During the measurement process, two counters count the standard signal and the measured signal simultaneously. First, the gate opening signal (preset gate rising edge) is given. At this time, the counter does not start counting, but waits until the rising edge of the measured signal arrives before the counter actually starts counting. Then, when the preset gate closing signal (falling edge) arrives, the counter does not stop counting immediately, but waits until the rising edge of the measured signal arrives before ending the counting and completing a measurement process. It can be seen that the actual gate time r is not strictly equal to the preset gate time r1, but the difference does not exceed one cycle of the measured signal. Assume that in an actual gate time r, the counter counts the measured signal as Nx, the counts the standard signal as Ns, and the frequency of the standard signal is fs. The frequency of the measured signal is as shown in formula (1).
(1)

Figure 2 is a logic block diagram of equal-precision frequency measurement. CNT1 and CNT2 are two controllable counters. The standard frequency signal fs is input from the clock input terminal CLK of CNT1, and the shaped measured signal fx is input from the clock input terminal CLK of CNT2. The CEN input terminal in each counter is the clock enable terminal, which controls the clock input. When the preset gate signal is high (the preset time starts), the rising edge of the measured signal passes through the output terminal of the D flip-flop, and the two counters start counting at the same time; similarly, when the preset gate signal is low (the preset time ends), the rising edge of the measured signal passes through the output terminal of the D flip-flop, and the counter counts are turned off at the same time.

Figure 2 Logic block diagram of equal-precision frequency measurement

System hardware design

The frequency meter is designed using ST's 32-bit processor STM32F103C8 as the main control chip and the high-reliability programmable logic device EPM240T100C5.

The functional features of STM32F103C8 are as follows: (1) The maximum frequency can reach 72MHz, with 128/64KB FLASH, 1.25DMIPS/MHz, and can access the memory with 0 wait cycles. (2) The power supply voltage range is 2.0~3.6V, with an embedded 8MHz high-speed crystal oscillator, and can also be supplied by an external clock. This system uses CPLD clock division supply. (3) The download mode can use the serial wire debug (SWD) interface and JTAG interface. This system uses the JTAG download interface.

The functional features of EPM240T100C5 are as follows: (1) Supports internal clock frequency of 300MHz. This system uses an active crystal oscillator with a frequency of 50MHz. (2) The on-chip voltage regulator supports 3.3V, 2.5V or 1.8V power input. This system uses a 3.3V voltage supply. (3) The download mode uses a 10-pin JTAG interface.

1 System hardware structure block diagram

The system controls the internal logic unit by controlling the STM32F103C8 microcontroller and sending data and commands to the CPLD chip EPM240T100 via the SPI bus. EPM240T100 uses an external active crystal oscillator 50MHz supply, and 12.5MHz is divided by 4 as the input clock of the CPU. The hardware structure of the system is shown in Figure 3. It includes the main control chip module, JTAG download module, reset circuit module, host computer display module, and measured input module.

Figure 3 System block diagram

2 Digital circuit design of the system

The principle of the microcontroller is shown in Figure 4. The processor of this system uses STM2F103C8, and the clock is divided by CPLD to supply the CPU. The data and commands are transmitted to CPLD via SPI, and then sent to the host computer for display via serial port RS232.

Figure 4 Schematic diagram of microcontroller