Solutions to improve FPGA design performance

As FPGA density increases, system designers can develop larger and more complex designs to maximize the density advantage. These large-scale designs are based on design requirements - the need to add new functions to existing applications such as wireless channel cards or line cards, or to reduce board area by combining two chip functions into one device, or to develop new designs for new applications.

These different designs contain existing code from the application or DSPs with high latency requirements. For these designs, the synthesis tool may not be able to optimize the design to its optimal state, resulting in longer delays in the critical path. The reason for the longer delays in the critical path is that the logic synthesis tool relies on estimated delays to synthesize the design.

These long-delay critical paths cause timing closure issues, resulting in performance degradation, forcing designers to rewrite the RTL code to improve these long-delay critical paths. In addition, users need to perform multiple iterations before they get the best RTL code that meets the timing specifications. This further delays the time to market.

Another problem that occurs in designs with high logic utilization is routing congestion. Designers must rewrite the RTL or try different settings in the place-and-route tool to improve the performance of these critical paths. This "trial and error" approach also causes product delays and reduces productivity.

These two issues are indeed great challenges for designers when they are performing timing closure, and timing closure becomes the main problem faced by system designers. One solution that can solve these two problems and improve performance at the same time is to use physical synthesis tools. Physical synthesis tools are provided by FPGA vendors and sometimes by third-party EDA tool vendors. The main function of physical synthesis tools is to improve timing closure (i.e. performance) by reducing the number of critical paths with the fewest number of iterations possible, thereby shortening the time to market.

The design flow of physical synthesis tools is shown in Figure 1 and works in the following manner. Logic synthesis tools use algorithms such as logic replication to replicate logic with large fan-outs and retime registers in longer logic paths to improve performance. Physical synthesis tools are different from logic synthesis tools in that they use similar algorithms to optimize critical paths using accurate delays and precise information. Logic synthesis tools rely more on global delay estimates, while physical synthesis tools use accurate delays.

Figure 1. Physical synthesis tools are part of the overall synthesis design flow.

Figure 1 shows that physical synthesis tools are also part of the overall synthesis flow. Physical synthesis tools are run after logic synthesis as part of the synthesis tool, and to further clarify the concept, it can be called early physical synthesis. In this flow, after logic synthesis, the tool models the placement and routing of the entire design, and again uses algorithms such as retiming and replication to improve the performance of critical paths. Some EDA vendors have developed tools based on this level of accuracy to solve the timing approximation problem.

Figure 2 shows another physical synthesis tool flow, which is called first after the placement phase in a typical flow. In this phase, the design is fully placed and delay estimates are performed on interconnect delays, so that critical paths can be predicted more accurately. By using the algorithms described above, critical paths can be improved to meet performance requirements. This can be done without modifying any line of RTL code. In the synthesis tool, it is possible to retime registers with inaccurate delays, resulting in performance degradation. By placing the design, the physical tool makes intelligent decisions, which helps predict which registers to retime to improve performance.

Figure 2. Physical synthesis tool settings in Quartus II design software.

Current FPGA architectures have two levels or hierarchies. The first level is the logic module, which is a group or collection of LAB logic cells. The second level of the hierarchy consists of logic cells, each of which contains a pair of registers, a pair of lookup tables, and a pair of full adders. In Altera FPGAs, this type of logic cell is called an adaptive logic module (ALM). These logic modules are stacked in an array and connected to on-chip memory blocks, DSP blocks, and IO blocks through a certain number of connections (routing), thus forming the FPGA architecture.

In a typical design flow, placement is performed twice. The first step is to place the entire design at the logic block level. Once completed, the placement algorithm places the logic at the logic cell level. Since physical synthesis tools rely on accurate information, it is easy to see that the physical synthesis results are improved after the second placement, producing better quality of results (QoR), thereby improving performance.

Another application where physical synthesis tools can improve productivity is when designing with an incremental design flow. In this approach, instead of using physical synthesis on the entire design, it is applied to each module. Because the physical synthesis tool focuses on the modules it needs, this not only helps to reduce compilation time, but also improves performance.

The physical synthesis tool is part of the Altera Quartus II place-and-route tool. The physical synthesis tool provides users with optimization options and effort levels to improve performance and efficiency. Some of the optimization options that users can control are listed below.

Physical synthesis for improved performance

Combinational logic physical synthesis: The tool further optimizes the combinatorial logic based on the accurate information. This option enables the Quartus II physical synthesis tool to resynthesize the combinatorial logic in the design, shortening the delay of critical paths and improving performance.

Asynchronous pipeline physical synthesis: Pipeline asynchronous signals such as load and clear. This option enables the Quartus II physical synthesis tool to insert pipeline registers on load and clear signals to improve performance.

Physical synthesis for registers

Retiming: Enables the tool to automatically balance registers. This option enables Quartus II to move registers between combinational circuits to improve performance.
Register Duplication: Duplicate registers with large fan-outs. This option enables Quartus II to duplicate registers based on placement information to improve performance.

Physical synthesis for adaptation

Combinational Logic Physical Synthesis: This is a second optimization of the combinatorial circuit. Quartus II performs a second optimization of the combinatorial circuit to help fit the design.
Complete Logic to Memory Mapping: This maps the combinatorial logic to memory to reduce area. Quartus II automatically maps the combinatorial logic to unused memory blocks to reduce area and fit the design.

Quartus II also provides an incremental design flow that supports both top-down and bottom-up design flows. This type of flow is used to reduce compilation time and improve performance

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Most companies today want to be the first to market with their products in the face of competition. As a proactive strategy, improving efficiency and time-to-market are key to the success of any product. Using physical synthesis tools to improve design performance means shorter design cycles and higher efficiency. Designers who can use these tools effectively will win.