FPGA Configuration Mode

FPGA has multiple configuration modes: the parallel master mode is a method of adding one FPGA to one EPROM; the master-slave mode can support one PROM to program multiple FPGAs; the serial mode can use a serial PROM to program the FPGA; the peripheral mode can use the FPGA as a peripheral of the microprocessor and program it by the microprocessor.

How to achieve fast timing closure, reduce power consumption and cost, optimize clock management and reduce the complexity of parallel design of FPGA and PCB have always been key issues that system design engineers using FPGA need to consider. Today, as FPGA develops towards higher density, larger capacity, lower power consumption and more integrated IP, system design engineers have to face new design challenges due to the unprecedented performance and capability level of FPGA while benefiting from these excellent performance.

Many projects use Altera's Cyclone series devices based on SRAM architecture. Like other FPGA devices, Cyclone devices provide programmable resources to users based on gate arrays, and the formation of their internal logic structure is determined by configuration data. These configuration data can be loaded into the SRAM inside the FPGA in a variety of modes. Due to the volatility of SRAM, the FPGA must be reconfigured every time it is powered on.

1 Cyclone FPGA Configuration Modes

There are three main configuration schemes for Cyclone series FPGA devices, including active serial (AS) configuration using low-cost configuration chips, passive serial (PS) configuration, and JTAG-based configuration. In actual applications, one of these schemes can be used to configure Cyclone series FPGA devices to achieve the functions that the user wants to achieve in programming.

The Cyclone series FPGA devices use SRAM cells to configure data. Since SRAM is prone to data loss after power failure, the configuration data must be downloaded immediately to the powered-on Cyclone device. Different configuration modes can use different dedicated configuration chips or data sources.

These three configuration modes are determined by the high and low levels of the Cyclone device's mode selection pins MSEL1 and MSEL0. If your actual application only requires a single configuration mode, you can connect the mode selection pin to the VCC terminal or the ground terminal. During the process of switching the pin, the device's operating state will not be affected. In any case, before reconfiguring, the level of the mode selection pin must be guaranteed to be valid.

2 Active Serial (AS) configuration of the configuration chip

In the AS configuration mode, new low-cost devices (such as EPCS1, EPCS4) are used. This dedicated configuration chip is a serial configuration device with permanent memory and a simple four-pin interface. Due to its low cost, it can solve the problem of high configuration device costs. The serial configuration chip provides a serial interface to access data. During configuration, the Cyclone FPGA reads data through the serial interface, decompresses the data if necessary, and configures the FPGA's SRAM cells. In this mode, the FPGA controls the configuration interface. This solution is called active serial configuration, or AS configuration for short. Schematic diagram of configuring a Cyclone FPGA device using AS mode

The dedicated serial configuration chip can be EPCS1 or EPCS4, where the storage space of EPCS1 is 1Mbits and the storage space of EPCS4 is 4Mbits. The designer can choose according to the size of the configuration file. The main configuration pins of the active serial configuration chip

DCLK, serial clock input, comes from the Cyclone FPGA device and provides the serial interface clock; DATA, serial data output, reads out data on the falling edge of DCLK; ASDI, control signal input, latches data on the rising edge of DCLK; nCS, enable input, low level is valid.

During system power-on, the two chips enter the power-on reset phase. Once the power-on reset is entered, the nSTATUS terminal is low level, and the chip is being reset; at the same time, the CONF_DONE terminal is low level, and the chip has not been configured. After the reset, the FPGA releases the nSTATUS terminal after a delay of 100ms. Due to the pull-up resistor, the terminal becomes high level, and the configuration state is entered at this time. Once the reset is exited, all user I/O terminals enter the tri-state state. The clock signal DCLK is generated by the FPGA inside, which is used to control the entire configuration cycle and provide a clock for the serial port circuit of the configuration chip. The frequency range of the clock signal is between 14MHZ and 20MHZ. When the falling edge of DCLK arrives, the FPGA outputs the control signal and the configuration chip outputs the configuration data; when the rising edge of DCLK arrives, the FPGA latches the configuration data and the configuration chip latches the control signal. After all the configuration data is received, the FPGA releases the CONF_DONE terminal, which is set to a high level through the 10K pull-up resistor, and begins to enter the initialization phase. Cyclone FPGA devices require 136 clock cycles to be strictly initialized. Then it starts to enter the user state, and the INIT_DONE pin jumps to a high level.

3 Passive Serial (PS) Configuration Based on MCU

Simplified circuit diagram of the passive serial configuration scheme of the Cyclone FPGA using a microprocessor. The microcontroller configuration process is very simple. The microcontroller only needs to use 5 I/O ports to connect to the FPGA. These 5 signal lines are: DATA0, DCLK, nCONFIG, nSTATUS and CONF_DONE.

The specific configuration process is as follows: ①nCONFIG=0, DCLK=0, keep for more than 2us; ②check nSTATUS, if it is 0, it means that the FPGA has responded to the configuration request and can start configuration, otherwise an error will be reported. Under normal circumstances, nSTATUS will be 0 within 1us after nCONFIG=0; ③nCONFIG=0, and wait for 5us; ④place data on DATA0, DCLK=1, delay; ⑤DCLK=0, check nSTATUS, if it is 0, report an error and start again; ⑥prepare the next bit of data, and repeat (4) and (5) until all data are sent out; ⑦at this time CONF_DONE should become 1, indicating that the configuration of the FPGA has been completed. If CONF_DONE is not 1 after all data are sent out, reconfiguration is required; ⑧after configuration is completed, send several cycles of DCLK to complete the initialization of the FPGA.

It is worth noting that the SOF or POF files generated by MAX+PlusⅡ or QuartusⅡ cannot be used directly to configure FPGA in single-chip microcomputers. Data conversion is required to obtain usable configuration data. In MAX+PlusⅡ or QuartusⅡ, there are data conversion options to convert .SOF files into .rbf files, and then write the .rbf files directly into a ROM or Flash area of ​​the single-chip microcomputer system. The starting address and length of this data are known, and the corresponding software can be written according to the above process.

4 Configuring Data Compression Methods

The Cyclone device is an FPGA device that supports decompressed configuration data, allowing the configuration data stored in the configuration chip or other memory to be compressed data. During configuration, this compressed data is sent to the Cyclone device and immediately decompressed to program the SRAM unit. Both the AS configuration mode and the PS configuration mode support compression, but the JTAG-based configuration mode does not support compression. Preliminary data shows that compression can reduce the configuration data bit stream by 35% to 60%, which can reduce data storage space and transmission speed as well as the cost of configuration equipment.

QuartusⅡ can generate compressed configuration files, which can reduce the transmission time of configuration chip and flash memory space and bit stream. The following uses QuartusⅡ5.1 as an example to introduce the operation methods of two compressed configuration files.

4.1 Method 1: Activate compression in the project program settings before programming.

First, click the Device item under the Assignments menu to pop up the Settings window. Then select the Cyclone device in the Family option, click the Device&Pin Options pop-up window below, select the Configuration window and click the Generate Compressed bitstreams option, and finally press the OK button to complete the settings.

4.2 Method 2: After designing the program, create the program file from the Convert Programming Files window and activate compression.

First, pull down the File menu and click the Convert Programming Files pop-up window. Select the file type Programming File type (POF, SRAM HEXOUT, RBF, or TTF), then select the configuration device for POF output files, and then select Add File to add a Cyclone SOF file. Select the file name and add it to the SOF Data area. Click the Properties option, then confirm, and finally press the Generate button to generate.

5 Conclusion

The hardware circuit of the serial configuration method is simple, the configuration process is easy to implement in software, and the engineering application is convenient. The technical parameters of the Cyclone series FPGA devices, such as logic resources and chip speed, can meet the project requirements, are cost-effective, and have certain scalability. This FPGA configuration implementation method is also suitable for combination with other CPUs and applied to other occasions, as long as the configuration requirements of software and hardware are strictly followed, so it has reference value in practical applications. Today, CPLD/FPGA has become a platform for digital system development, and will continue to improve and improve in the future in terms of high integration, large capacity, low cost, low voltage, low power consumption, diversified resources, applicable to system on chip (SOC), deep submicron technology, various software and hard IP libraries, and practical application of dynamic reconfigurable technology.