Design of Direct Sequence Spread Spectrum System Based on FPGA

Abstract Aiming at the shortcomings of general wireless communication systems in terms of poor anti-interference, anti-noise and anti-multipath capabilities, a direct sequence spread spectrum system design based on FPGA is proposed. The design uses a 63-bit pn code as the code sequence for spread spectrum modulation. At the transmitting end, the information code is spread spectrum modulated; at the receiving end, the received spread spectrum modulated signal is despread, which enhances the anti-interference and reliability of the system. At the same time, in Altera's QuartusⅡ software, the circuit design and implementation are carried out by combining the hardware description language VHDL and the schematic diagram. By cutting the circuit to Altera's CycloneIII EP3C10E144C8N chip for debugging, the feasibility of the spread spectrum system is verified.
Keywords Spread spectrum; pn code; FPGA

Due to the excellent characteristics of spread spectrum communication system such as good anti-interference, strong anti-multipath fading, high-precision measurement, multiple access multiplexing, etc., it has been rapidly developed and widely used for many years.

1 Basic principle of direct spread spectrum system
Direct spread spectrum communication is to use a high-speed spread spectrum sequence at the transmitting end to expand the spectrum of information data, including two processes: pseudo code modulation and carrier modulation. It is different from the common narrowband communication method in that the information data becomes a broadband signal after spectrum expansion, and then is restored to a narrowband signal through correlation processing and then demodulated to obtain the information data. Therefore, it has two major characteristics: signal correlation processing and pseudo-random coding modulation.

The composition principle of the direct spread spectrum communication system is shown in Figure 1. The information input at the transmitting end is first modulated into a digital signal, and then the spread spectrum code sequence generated by the spread spectrum code generator modulates the digital signal to widen the signal spectrum. The widened signal is then modulated to the radio frequency and sent out. At the receiving end, the received broadband radio frequency signal is frequency-converted to the intermediate frequency, and then de-correlated and de-spread by the locally generated spread spectrum code sequence that is the same as the transmitting end, and then demodulated and restored to the original information output.

2 System Overall Plan
In the transmitting system, first generate an 8-bit serial information code data_in, and then perform modulo-2 addition with the spread spectrum pseudo code sequence from the pn code generator to complete the spectrum expansion of the signal and obtain the spread spectrum signal data_kuo. After the pn code is synchronously captured at the receiving end, the spread spectrum modulated signal is XORed with the local synchronous spread spectrum sequence to obtain the de-spread signal data_jie, and the waveforms of data_kuo and data_jie are compared to verify the effect and feasibility of the system spread spectrum de-spreading.

3 System modular design
3. 1 Generation of information code input module
The function of this module is to use the 8-bit shift register to shift and output the 8-bit information code under the control of the clock signal. clr is the loading signal. When clr=0, the 8-bit information code is read in parallel from the code switch and loaded into the internal 8-bit register. When clr=1, the input 8-bit information code is serially shifted and output under the control of the clock signal.
The simulation results are shown in Figure 2. The data information before spread spectrum is 11000110B.

3.2 Digital design of pn code generator
As mentioned above, the pn code generator of this system adopts m-sequence generator. The feedback logic of n-level linear shift register can be expressed by characteristic polynomial f(x)=c0+c1x+c2x2+…+cnxn. The m-sequence generator uses 6-level shift register, that is, n=6. The feedback coefficient obtained by table lookup is 103, so its corresponding characteristic polynomial is f(x)=x6+x+1. Feedback is introduced from the 1st and 6th levels. The shift register feedback principle diagram is shown in Figure 3.

The 6-level m-sequence generator can generate a PN code sequence with a period of 63. If the register starting sequence is all zero, the output sequence will also be all zero, which will cause the PN code generator to enter a deadlock state. Therefore, in order for the PN code generator to work properly and generate the expected PN sequence, it must be ensured that at least one of the registers is 1 at the beginning. The 63-bit PN code simulation diagram is shown in Figure 4.

3.3 Comprehensive simulation of spread spectrum modulation and demodulation module
In practical applications, in order to achieve the purpose of data symbol spread spectrum, the usual practice is to multiply the signal to be transmitted with a spread spectrum code sequence, and the spread spectrum sequence has a much narrower time width than the data bit, so that the spread spectrum sequence has a much higher frequency band than the data sequence.
The schematic diagram of the overall system design is shown in Figure 5. In the design of this system, both the transmitter and the receiver work in the data symbol synchronous modulation mode, that is, the pn code sequence is aligned with the data symbol level change edge, and each symbol is repeated once; at the receiver, a pn code sequence is synchronized within a data symbol time, and the data symbol is synchronized while capturing a pn code sequence. This not only shortens the capture time, but also eliminates the clock synchronization system composed of a phase-locked loop in general narrowband digital communication, simplifying the system design.

In this design, a data symbol is synchronized with a 63-bit pn code sequence, pn is the 63-bit m sequence generated by the pn code generator module, data_in is the serial information code generated by the information code input module, in this figure it is the 11000110 data symbol, and data_kuo is the output of this spread spectrum module. At the transmitting end, the result of the spread spectrum is actually a time domain multiplication of the two, or a modulo-2 sum, and a data symbol is synchronized with a 63-bit pn code sequence, completing the symbol synchronization modulation mode, and then modulo-2 addition is performed with the pseudo code sequence from the pn code generator to complete the spectrum expansion of the signal. At the receiving end, data_kuo is modulo-2 summed with the local synchronous pn code to form a despread signal, and the despread output signal is data_jie.

The comprehensive simulation diagram of spread spectrum despreading is shown in Figure 6. Among them, data_in is the serial input binary number 11000110, the clock signal of the information code input is clk, the clock signal of the pn code generator is elk1, pn is the generated 63-bit pn code sequence, data_kuo is the code sequence after spread spectrum, and data_jie is the signal after despreading, thus realizing the despreading of the signal.

4 FPGA implementation of the system
The system selects CycloneIII series FPGA (EP3C10E144C8N) produced by Ahera. This CycloneIII FPGA of Ahera has 75% lower power consumption than the previous generation of FPGA. It has a total of 144 pins. These I/O pins support 6 single-ended signal standards and 8 differential standards. It contains 10 kbit logic units (LEs), 23 digital signal processing (DSP) multipliers, and 400 kbit of memory. The cost per logic unit of the CycloneIII series is 20% lower than that of the previous generation of products, enabling designers to use FPGAs more in cost-sensitive applications.
Download the VHDL source program to the FPGA through the JTAG port. After configuring the FPGA pins, use the pin header to lead out the FPGA pins, connect the FPGA output pins to the oscilloscope inputs, and observe the system waveform as shown in Figure 7. It can be seen from the figure that the FPGA output waveform is consistent with the simulation diagram, thus verifying the correctness and feasibility of the system VHDL program. In addition, due to the high system clock frequency, the waveform has a relatively obvious overshoot phenomenon.

5 Conclusion
A design of a direct sequence spread spectrum system based on FPGA is proposed, aiming to make the wireless communication system have strong anti-interference and reliability. On the Altera's Quartus II software platform, the circuit design is implemented by combining the hardware description language VHDL and the schematic diagram, and the program is downloaded to the FPGA. The output waveform is observed by an oscilloscope, and the spread spectrum despreading performance of this system is observed by the output waveform results.