25kW electric vehicle SiC DC fast charging design guide: experience summary

In our series of reference design documents, we describe in detail the development process of the 25 kW DC fast charging module. This white paper mainly discusses the tips and tricks of hardware and firmware design and debugging stages in the development and testing of 25 kW DC fast charging modules. We'll cover how to test and fine-tune desaturation protection, analyze the causes of SiC MOSFET drain voltage ringing, and the benefits of adding snubber capacitors. Also consider how to use lower power equipment than the device under test (DUT) in loopback testing to test the DUT. Finally, we will discuss the phase-shifted dual active bridge control algorithm design.

Introduction

Figure 1 below is a high-level block diagram of a 25 kW electric vehicle DC fast charging system, which mainly consists of a PFC stage and a phase-shifted dual active bridge DC-DC stage.

Figure 1 High-level block diagram of a 25 kW electric vehicle DC charging pile

During any power converter design process, it is important to implement hardware protection. In fact, the power switching device is the core of the converter, and designers need to ensure that the system provides protection functions in various specific scenarios. In these scenarios, overvoltage and overcurrent protection are basic requirements. These two types of protection can be implemented in a variety of ways: a relatively simple method, such as adding resistance-capacitance components in key loops to form a so-called buffer (Snubber), which helps limit voltage peaks; another more complex method is Blocks device operation when transient conditions exceed predetermined criteria.

When taking this approach, such as the one we used when developing dual active bridge converters, adding voltage comparators with specified thresholds and hysteresis on both sides of the converter to implement overvoltage protection, the DC-Link Blocks the gate driver in case of overvoltage.

A similar approach applies to overcurrent protection solutions. The problem can be easily solved by using a gate driver with built-in overcurrent protection function. Using the NDC57000 gate driver with desaturation protection (DESAT) function can reduce BOM costs and improve product market competitiveness. In the next section, we present the measurement and evaluation of PFC-level and DAB DCDC-level DESAT thresholds during the hardware startup test phase, which is essential before control firmware (FW) debugging. At the DAB DC-DC stage, we focus on enhancing the DESAT protection function to achieve a wide output (200 V to 1000 V) operating voltage range.

The key hardware features in fully digitally controlled power converters are hardware protection, overcurrent and overvoltage protection, designed to prevent power semiconductor devices from dissipating excessive power during overcurrent or short circuits. This prevents overvoltage spikes that could damage the power semiconductors. Hardware protection is crucial during the start-up and debugging stages of the control algorithm, because unpredictable MOSFET switching often occurs at this time, causing the power device to burn out, which requires time and cost to deal with, which is very troublesome.

PFC grade DESAT protection

The NCD57000 isolated gate driver used in the PFC stage features DESAT protection, which facilitates the overcurrent protection design of the PIM SiC MOSFETs used. "25 kW SiC DC Fast Charging Design Guide (Part 6): Gate Drive System for Power Modules" describes the design process. We evaluated the DESAT functionality during the hardware startup phase and measured the DESAT action threshold current and SiC MOSFET soft-off time.

The measurement principle for DESAT action current evaluation of high-voltage side SiC MOSFET is shown in Figure 2; the left side is the high-voltage side, and the right side is the low-voltage side SiC MOSFET measurement. We chose the same test voltage as the applied DC-LinkDC-Link voltage, which is 800 V. The high-voltage side SiC module under test is turned on through the gate test pulse, causing DESAT protection to operate. Assuming negligible DC resistance, the current rise di/dt through the SiC MOSFET under test is limited only by the series PFC inductance of 150μH. The current rise can be expressed by the following equation.

Figure 2 PFC level DESAT action current hardware startup test

High-side SiC MOSFET (left) and low-side SiC MOSFET (right)

In "25 kW SiC DC Fast Charge Design Guide (Part 6): Gate Drive System for Power Modules", for 800 V DC-LinkDC-Link voltage, we calculated the theoretical DESAT threshold current value to be 85÷115 A; The calculation process is explained in detail in the application manual AND9949, and the measurements are performed at room temperature of 25 °C. It is important to note that the DESAT threshold level also depends on the temperature of the components in the SiC MOSFET, gate driver and DESAT protection circuit.

According to the measurement results in Figure 3, the SiC MOSFET has an on-time of 25 to 27 ns and a soft-off time of 700 to 710 ns (when DESAT is operating). The DESAT action threshold was measured at 75 A on the high voltage side and 72 A on the low voltage side. We evaluated all prototype designs and measured DESAT thresholds, resulting in a range of 68 A - 117.7 A. Since the maximum phase current of the PFC stage should be 70 A at 26.5 kW (1.5 kW is the power margin of the 25 kW PFC stage) and 207 VRMS, we increase the DESAT threshold in the PFC stage by 20% so that at 85 A - Activated at minimum current threshold in the 90 A range.

For commercial mass-produced products, an evaluation description is essential and measurements should be made with sufficient samples to allow a reliable assessment of the changes caused by the numerical tolerances of the electronic components used.

Figure 3 DESAT trip level measurement

High-side (left) and low-side (right) SiC MOSFETs

To understand the effect of ambient temperature on the DESAT current threshold level, the same sample was measured at 25 °C and 50 °C; the DESAT action threshold increased by 5.4 A. The measurement results under two temperature conditions are shown in Figure 4. This measurement shows how important it is to design DESAT protection over the entire operating voltage range and over the entire temperature range.

Figure 4 DESAT operating current at 25 ℃ (left) and 50 ℃ (right)

Note: The test in Figure 2 only evaluates the action level of one SiC MOSFET when a short-circuit fault occurs; the test does not evaluate the short-circuit situation of the upper and lower arms when current flows from the high-voltage side to the low-voltage side SiC MOSFET. When a bridge arm short circuit occurs, the current is no longer limited. DESAT protection cannot effectively protect SiC MOSFETs because the main limiting factor (i.e. the series PFC inductor) limits the current rise as shown in equation (1), allowing DESAT to react at the desired current level and avoid large currents from continuing to flow. through MOSFET.

DAB DCDC grade DESAT protection enhancement

Like the PFC stage, the dual active bridge converter DCDC stage also uses the NDC57000 gate driver with DESAT protection. In principle, this protection uses the changing voltage drop across the power path terminals to monitor the level of current flowing through the driving switching device. Of course, the characteristics of the switching device must be understood for proper overcurrent protection configuration. While data sheets provide basic information, they are often not detailed and application-specific, making accurate device selection impossible. While prototype testing is important, circuit simulation tools can also be helpful during the design process. As shown in the partial circuit diagram of Figure 5, the recommended driver circuit follows the NCD57000 data sheet recommendations.

Figure 5 NCD57000 gate drive circuit diagram

Although calculating the desaturation threshold resistor (R27A in Figure 5) may seem simple, it is not necessarily so because the RDS,ON parameter is not constant; it varies with the gate voltage and the instantaneous current flowing through the device. Simply combining these two correlations to obtain the actual RDS value for use in the RDESAT value calculation is not a trivial task based on the data provided in the device data sheet. It will be easier to implement if there is a device simulation model.

Since the complete simulation model of the NCD57000 has not yet been published, we built a simplified model of its desaturation function that can be used in conjunction with the switching device. Simulation results show that the DESAT static threshold depends on resistor R1. The resistance of the primary side half-bridge is initially selected to be 14.3 kΩ on the primary side, and the resistance value of the secondary side half-bridge is 13.3 kΩ, because under certain conditions, the secondary side current will be slightly higher. Figure 6 shows the simulated gate circuit diagram.

Figure 6 NCD57000 gate driver simulation circuit diagram

Figure 7 shows the simulated static threshold of DAB DESAT protection under different R1 resistance values.

Figure 7 DAB DESAT protection static threshold simulated under different R1

Like the PFC stage, the desaturation protection of the DAB DCDC stage has also been proven. The figure below is a simplified schematic diagram of the power stage on both sides, including the power inductor and transformer.

Figure 8 Simplified diagram of the power stage on both sides, including power inductor and power transformer

The number of possible fault conditions is relatively large. Therefore, we selected the following possible scenarios for desaturation protection testing to limit the number of tests and ensure a simple and reproducible setup:

• Primary side primary switch - secondary side short circuit simulation (Figure 9)

Figure 9 Secondary side short circuit simulation secondary side

• Secondary side switch – primary side short circuit simulation primary side (Figure 10)