AD10242 dual-channel high-speed ADC and its application

　　The AD10242 circuit is a high-speed analog-to-digital converter (ADC) launched by the American ADI Company. With a sampling speed of up to 40MHz per second, it is the latest high-speed, high-performance, low-power 12-bit dual-channel analog-to-digital converter. It is powered by ±5.0V power supply, and its input signal can be either bipolar or unipolar. On-chip tracking/protection amplifier (T/H), reference power supply and output buffer. The two channels in the chip are completely independent, each with its own decoding and analog input. Each channel uses laser correction gain and offset matching to ensure that the crosstalk between the two channels is better than 80dB. This circuit is undoubtedly an ideal choice for small-sized, high-speed, highly integrated embedded processing systems. 　　

　　1 AD10242 core introduction 　

　　Each channel in the AD10242 integrates three monolithic devices, AD9632, OP279, and AD9042, as well as multiple resistors and decoupling capacitors. The internal structure of AD10242 is shown in Figure 1. Its core device is the AD9042. The input signal can be selected from ±0.5V, ±1.0V, and ±2.0V through a precision resistor divider. The resistor divider method can be used to protect the internal amplifier AD9632 from providing a 0.4V input voltage. The AD9632 is a DC-coupled horizontal phase shift circuit provided to the AD9042 analog-to-digital converter. The amplifier is configured in a non-invertible mode, where the AC signal is modified to provide a constant input to the ADC, centered around the AD9042's internal reference voltage. AD10242 can be used in signal processing application systems such as radar signal processing, communication receivers, FILR signal processing, and secure communications. 　　

　　The core device AD9042 in the AD10242 is based on AD's high-speed complementary bipolar processing technology and adopts an improved multi-channel parallel structure design to ensure a distortion-free dynamic range of 80dB on a 20MHz bandwidth, with a typical signal-to-noise ratio of 68dB. . The AD9042 analog-to-digital converter adopts a two-level conversion mode. This design can ensure 12-bit accuracy at lower power without using laser correction. Its 1V (peak-to-peak) single-ended analog input and 2.4V midpoint voltage form a single-ended input differential output amplifier A1 and two input signals. The A1 output can be used to drive the first tracking/protection amplifier (TH1), and a high state on the encoding input can place TH1 in a hold state. The hold signal of TH1 is used to generate the input of a 6-bit coarse conversion ADC value. The 6-bit fine conversion value data can drive a 6-bit DAC, and the 6-bit coarse conversion can be simulated by the TH2 input at the input end of TH3. The values ​​are subtracted to generate a residual difference signal, which is amplified by the difference amplifier A2 through the hold amplifier (TH3) in the next clock cycle, and then converted by the 7-bit precision conversion ADC to generate a 7-bit data code, one of which Code overlap is used to adjust the first 6-bit ADC generation. The 6-bit fine conversion code and the 7-bit fine conversion code are combined and corrected in the digital error correction logic to produce the output code (12-bit parallel data), which is output in two's complement format in a CMOS-compatible mode. 　　

　　2 Pin functions of AD10242 　　

　　3 Application of AD10242 　　

　　3.1 Signal input of AD10242 　　

　　The analog input of the AD10242 can be designed as a DC-coupled bipolar input (±0.5V, ±1.0V, ±2.0V), or it can be configured as a unipolar input through an external resistor. Connect a 2.43kΩ variable resistor between UPOS and UCOM (can be used for offset calibration) to achieve positive input of 1V, 2V, 4V. Connect a 2.43kΩ variable resistor between UNEG and UCOM to achieve - 1V, -2V, -4V negative input. 　

　　3.2 Coding signal input of AD10242 　

　　The logic interface of AD10242 is compatible with TTL and CMOS logic. It relies on the beat of the encoded signal ENCODE to collect data on its rising edge. The signal source driving the ENCODE pin must be clean and non-oscillating, because the oscillating signal source will reduce the SNR index. , the timing is shown in Figure 2. 　

　　The encoded signal input terminal of AD10242 can be connected to the differential input stage. When ENCODE or other input signals are not connected, the input stage bias voltage is 1.6V. For TTL or CMOS applications, the code signal source should be connected to ENCODE. ENCODE can be connected to ground through a low value inductor or high frequency chip capacitor.

　　Figure 3 shows the circuit diagram of the interface connection between AD10242 and DSP.

　　3.3 Power supply 　　

　　Since the AD10242 uses an analog ±5V power supply and a digital ±5V power supply, it is best to feed them separately during design, because fast digital oscillation may couple conversion noise back to the analog power supply. Each power supply pin must be connected to a 10μF tantalum capacitor and a 0.01μF chip state capacitor to decouple each power supply. The decoupling components should be as close as possible to the A/D converter. The decoupling of the analog power supply must be connected to the analog ground point first, and the decoupling of the digital power supply must be connected to the digital ground point first. The interconnection between analog ground and digital ground can only occur at the power common terminal. 　　

　　4 Hardware interface with DSP 　

　　The basic simulation of real-time signal processing system generally adopts the "ADC+CPU (DSP, ARM, etc.) + DAC" structure. The design is generally to first convert it into a digital signal through the ADC subsystem, and then use the CPU subsystem to The digital signal is processed, and then the processed digital signal is converted back into an analog signal through the D/A converter subsystem. This system is a traditional real-time signal processing system based on DSP. This system uses AD10242 as the ADC acquisition module, which can ensure the system's 10-bit accuracy, 28MHz sampling speed, 2-channel parallel acquisition and ±2.0V analog input requirements. Since the DSP uses TI's TMS320C6701 high-performance floating-point processor, its core voltage is 1.8V and the peripheral I/O voltage is 3.3V. Therefore, a driver circuit must be added after the ADC. This design uses the SN74LVC164245 driver.