Fully digital phase-locked loop circuit design using VHDL

The working principle of the all-digital phase-locked loop is described, and a method of designing the all-digital phase-locked loop using VHDL technology is proposed. The method is implemented using complex programmable logic devices (CPLDs), and the design process and simulation results of the main modules of the system are given.

0 Introduction

The fully digital phase-locked loop (DPLL) avoids the disadvantages of analog phase -locked loops such as temperature drift and susceptibility to voltage changes. It has the advantages of high reliability, stable operation, and convenient adjustment. It is widely used in modulation and demodulation, frequency synthesis, FM stereo decoding, image processing, and other fields. With the development of electronic design automation (EDA) technology, large-scale programmable logic devices (such as CPLD or FPGA ) and VHDL language are used to design dedicated chips ASIC and digital systems, and the entire system can be integrated into one chip to realize system SOC and form an on-chip phase-locked loop. The following introduces a solution for designing DPLL using VHDL technology.

1 Basic Structure of DPLL

The structure block diagram of the all-digital phase-locked loop is shown in Figure 1. It consists of three parts: a digital phase detector, a digital loop filter, and a digitally controlled oscillator.

The digital phase detector in the design adopts an XOR gate phase detector; the digital loop filter is composed of a variable modulus reversible counter (the modulus K can be preset); the digital controlled oscillator is composed of an add/subtract pulse controller and a divide-by-N counter.

The clock frequencies of the reversible counter and the add/subtract pulse controller are Mf0 and 2Nf0 respectively. Here f0 is the center frequency of the loop, and in general M and N are integer powers of 2. The clock 2Nf0 is obtained by dividing the H (= M/2N) counter.

2 Principle and Implementation of Digital Phase-Locked Loop

The principle of the fully digital phase-locked loop is shown in Figure 2, where: clk is the clock frequency, equal to 32f0; U1 is the input, with a frequency of f0; j is the output of the XOR gate phase detector, which serves as the direction control signal of the variable modulus reversible counter; out is the output of the add/subtract pulse controller; U2 is the output of the DPLL, with a phase-locked frequency of f0 and a phase difference of Π/2 from the input U1; D, C, B, and A can preset the modulus of the variable modulus reversible counter, which varies in the range of 0001-1111, and the corresponding modulus varies in the range of 2.3-2.17; En is the enable terminal of the reversible counter.

Figure 2 Schematic diagram of digital phase-locked loop

2.1 Design of phase detector

The XOR gate phase detector is used to compare the phase difference between the input signal u1 and the output signal u2 of the numerically controlled oscillator. Its output signal ud is used as the counting direction control signal of the reversible counter. When ud is low (u1 and u2 have the same polarity), the reversible counter counts "up". On the contrary, when ud is high, the reversible counter counts "down".

When the loop is locked, fi and fo are orthogonal, and the output signal Ud of the phase detector is a square wave with a duty cycle of 50%. At this time, the phase error is defined as zero. In this case, the cycles of "add" and "subtract" of the reversible counter are the same. As long as the k value of the reversible counter is large enough (k> M/4), no carry or borrow pulse will be generated at its output. The add/subtract pulse controller only divides its clock 2Nfo by two to keep the phases of fi and fo orthogonal. When the loop is not locked, if Ud = 0, it makes the reversible counter count upward and causes a carry pulse to be generated. The carry pulse acts on the "add" control terminal i of the add/subtract pulse controller, and the controller adds half a clock cycle, that is, one pulse, in the process of dividing by two. On the contrary, if Ud = 1, the reversible counter counts down and sends the reversed release pulse to the "minus" input terminal d of the plus/minus pulse controller. Thus, the controller subtracts half a clock cycle, i.e., one pulse, during the frequency division process. This process occurs continuously. After the output of the plus/minus pulse controller is divided by N, the phase of the local estimation signal U2 is adjusted and controlled, and finally reaches a locked state.

The corresponding waveform of the XOR gate phase detector when the loop is locked and the phase error reaches the limit is shown in Figure 3:

Figure 3 XOR gate phase detector working waveform

2.2 Design of digital loop filter

The digital loop filter is composed of a variable modulus reversible counter. The counter is designed as a 17-bit programmable (variable modulus) reversible counter with a counting range of , which is controlled by an external setting DCBA. Assuming that the system works without phase difference, according to the principle of phase-locked loop, the phase difference between u1 and u2 is 0, and the output of the XOR gate phase detector is a symmetrical square wave, as shown in Figure 4 (a). Therefore, the reversible counter counts up or down in the same time interval. As long as k is large enough, the count starting from zero will not overflow or be insufficient.

If u1 starts to lag behind u2, the XOR gate output is asymmetric, then the counter count time is longer than the count time, and as a result, the counter will overflow over time and generate a carry pulse. On the contrary, if U1 starts to lag behind U2, the counter will generate a borrow pulse. The carry and borrow pulses can be used to control the DCO, so that the number of pulses output by the DCO is added or deleted according to the carry and borrow, which actually changes the output frequency of the DCO. The design of the variable-mode reversible counter is completed by VHDL, and the program is as follows:

library ieee ;

use ieee.std_logic_1164.all;

use ieee. std_logic_unsigned. all;

entity li is

port (clk,j,en,d,c,b,a:in std_logic;

r1 ,r2 :out std_logic) ;

end li ;

architecture behave of li is

signal cq,k,mo:std_logic_vector (16 downto 0);

signal cao1,cao2:std_logic;

signal instruction:std_logic_vector (3 downto 0);

begin

instruction < = d &c &b &a ;

with instruction select

mo <="00000000000000111"when"0001",

"00000000000001111"when"0010",

"00000000000011111"when"0011",

"00000000000111111"when"0100",

"00000000001111111"when"0101",

"00000000011111111"when"0110",

"00000000111111111"when"0111",

"00000001111111111"when"1000",

"00000011111111111"when"1001",

"00000111111111111"when"1010",

"00001111111111111"when"1011",

"00011111111111111"when"1100",

"00111111111111111"when"1101",

"01111111111111111"when"1110",

"11111111111111111"when"1111",

"00000000000000111" when others ;

process (clk ,en ,j ,k ,cq)

begin

if clk'event and clk = '1'then

k <= mo ;

if en = '1' then

if j = '0' then

if cq < k then cq < = cq + 1;

else cq < = (others = > '0') ;

end if ;

else

if cq > 0 then cq < = cq - 1 ;

else cq <= k ;

end if ;

end if ;

else cq < = (others = > '0') ;

end if ;

end if ;

end process;

process (en ,j ,cq ,k)

begin

if en = '1' then

if j = '0' then

f cq = k then cao1 < = '1';

else cao1 <= '0';

end if ;

cao2 <= '0';

else

if cq="00000000000000000"then

cao2 <= '1';

else cao2 <= '0';

end if ;

cao1 <= '0';

end if ;

else cao1 < = '0';cao2 < = '0';

end if ;

end process;

r1 <= cao1 ; r2 <= cao2 ;

end behave ;

The simulation waveform of the variable-mode reversible counter (taking k = 24) is shown in Figure 4.

Figure 4 Simulation waveform of variable-mode reversible counter (k = 24)

2.3 Design of digital controlled oscillator

The digital controlled oscillator is composed of an add/subtract pulse controller and a divide-by-N counter. The add/subtract pulse controller is actually an increment-decrement counter type DCO. It is used in conjunction with a loop filter. If there is no carry or misalignment in the loop filter, the add/subtract pulse controller divides the clock 2NFo by two. When a carry pulse is input to the increment input terminal (I = 1) of the add/subtract pulse control, a clock pulse is added to the output pulse through the counter. Conversely, when a borrow pulse is input to the decrement input terminal (D = 1) of the add/subtract pulse control, a clock pulse is subtracted from the output pulse. Therefore, the output frequency can be changed by borrow and carry pulses, and the output frequency can be controlled within a given range by the highest frequency of carry and borrow pulses. The add/subtract pulse controller is composed of a D flip-flop and a JK flip-flop. According to the functional analysis, the corresponding VHDL program can be designed. The simulation waveform after running is shown in Figure 5:

Figure 5 Add/subtract pulse controller simulation waveform

3 Experimental simulation results and analysis

In this design, the all-digital phase-locked loop is implemented by software. By writing the module in VHDL language, simulating and instantiating it, the entire circuit is gradually implemented from bottom to top , and finally the overall simulation download is successful.

The loop is locked (k = 2^5), and the DPLL system simulation waveform is shown in Figure 6.

Figure 6: Simulation waveform when the loop is locked (k = 2^5)

It can be seen from the simulation waveform that the simulation time when u1 and u2 reach the locked state is 70us.

When the loop is locked (k = 27), the simulation waveform of the DPLL system is shown in Figure 7:

Figure 7. Waveform simulation diagram when the loop is locked (k = 27)

In this case, the simulation time for u1 and u2 to reach the locked state is 180ms.

Obviously, the larger the modulus k is, the longer it takes for the loop to enter the locked state. If k is too large, it is beneficial to suppress noise and reduce phase jitter, but at the same time it increases the time it takes for the loop to enter the locked state. On the contrary, if k is too small, it can accelerate the locking of the loop, but the ability to suppress noise will be reduced.

4 Conclusion

The full digital phase-locked loop designed with VHDL has the advantages of flexible design, convenient modification and easy implementation, and can be made into an embedded on-chip phase-locked loop. The modulus of the counter in this type of digital phase-locked loop can be modified at will, so that the loop can be designed flexibly and to the maximum extent according to different situations.