Design of a general control platform for high power converters based on dual DSP

This paper introduces a universal control platform for high-power converters. It is a dual-DSP control system architecture with TMS320C6713B as floating-point arithmetic core and TMS320F2812 as fixed-point system control core. The hardware circuit and software program design of each module of the system are analyzed in detail. The system control platform has strong computing performance, good versatility and scalability, and has been successfully applied to the 400 kVA shore power supply prototype.

Converter technology and modern power electronics technology are widely used in AC variable frequency speed regulation, power supply, power transmission and distribution, power quality control, etc. High-power converters have the same or similar main circuit structure. Its controller structure is basically composed of signal conditioning circuit, A/D conversion circuit, microprocessor (DSP or single-chip microcomputer ), PWM generator, switch input and output, and communication with the host computer (serial port or network port) circuit. Therefore, the converter device controller has a wide range of commonalities. Here, a design scheme for a high-power converter general control platform based on a dual DSP (TMS320C6713B and TMS320F2812) architecture is proposed. Compared with the converter-specific controller, it has stronger versatility, is conducive to the modular design of converter controller software and hardware, and promotes the research on converter device control algorithms, shortening its product development cycle.

1 Overall system design

Figure 1 is a control system block diagram of the control platform. The system is designed with TI's dual DSP processors TMS320C6713B (floating-point DSP) and TMS320F2812 (fixed-point DSP) as the core controller. The floating-point DSP TMS320C6713B expands the AD bus , realizes floating-point operations, and HPI interface online programming; while the fixed-point DSP TMS320F2812 event manager realizes PWM control, speed acquisition, switch state control, fault detection, and some communication functions. The dual-port RAM IDT70V25 realizes dual DSP communication, has IDT70V25 8 K×16 bit shared area, logic busy and interrupt access arbitration mode. At the same time, the control system is expanded with 1 FPGA to realize network communication, ISP, LCD display, keyboard input, etc.

2 System Hardware Circuit Design

2.1 Collection circuit

2.1.1 Current and voltage detection circuit

In order to effectively adjust the output voltage, current and power factor of the converter main circuit, the output signals such as three-phase voltage, current signals and DC link voltage are collected respectively.

In view of the sampling accuracy and sampling rate requirements of the control platform, the AD7865 A/D converter of ANALOG Device was selected. This device is a high-speed, low-power, 4-channel synchronous sampling 14-bit A/D converter, powered by +5 V; it has a 2.4μs successive approximation A/D converter, 4 tracking/holding amplifiers, an internal 2.5 V reference voltage, an on-chip clock oscillator and a high-speed parallel interface; it synchronously samples 4-channel input signals, allowing two input ranges of ±10 V and ±5 V, and the ±10 V input voltage is selected here. Each AD7865 in this design can collect 4 analog signals at the same time. Figure 2 shows some signal conditioning circuits of AD7865.

The three-phase line voltage, three-phase current, DC voltage and current, and input and output filter line current of the main circuit input and output sides are collected by Hall sensors and output as current. The current signal output by the Hall sensor is input into the A/D sampling circuit through the slot and converted into a ±15 V voltage signal through a precision resistor . The voltage signal is converted into a +10 V voltage signal through an active low-pass filter with amplitude modulation function, and then sent to the analog input terminal of AD7865 through an inverter. The control signals of AD7865, such as BUSY, are realized by the EMIF bus of TMS320C6713B through the logic decoding of EPM570T100 CPLD.

2.1.2 Motor speed detection circuit

The universal control platform of the converter uses an incremental photoelectric encoder to design a motor speed meter. The photoelectric encoder outputs two - phase signals QEPI and QEP2 with a pulse waveform difference of 90°. When rotating forward, QEP1 phase leads QEP2 phase; when rotating reversely, QEP2 phase leads QEP1 phase. The motor speed is measured according to the frequency of the optical pulse output by the photoelectric encoder. The incremental rotary encoder rotates coaxially with the motor under test and outputs three differential signals A, B, and Z. The phase difference between the two groups of pulses A and B is 90°, which can easily determine the direction of rotation, and the Z path is the reference point positioning of one pulse per rotation. These three differential signals are converted into logic signals by MAX490ESA, and then isolated by high-speed optical coupler 6N137 and sent to the orthogonal pulse encoding circuit of TMS320F2812 to measure the motor speed. The differential signal input circuit of the incremental rotary encoder is shown in Figure 3.

2.2 Microprocessor Core Circuit

The core unit of the general control platform, the main controller, needs to realize the fixed-point and floating-point operations, analog sampling, protection, communication and other functions of the system. Therefore, the main controller architecture of floating-point DSP + fixed-point DSP + FPGA is adopted. Among them, the floating-point DSP TMS320C6713B expands AD7865 through the CPLD EPM570T100 bus to complete the control parameters such as three-phase voltage, current, frequency and DC voltage; primary complex floating-point operations such as coordinate transformation; control algorithm implementation and operation status record storage, etc. The fixed-point DSP TMS320F2812 mainly realizes peripheral functions and some fixed-point operations. TMS320-F2812 reads the operation results of TMS320C6713B through the dual-port RAM IDT70V25; realizes SPWM and SVPWM through the event manager modules EVA and EVB; fault status detection and protection; system main circuit switch status input and output, etc. FPGA EP2C20Q240 is connected to TMS320C6713B through HPI interface and to TMS320F2812 through McBSP interface. The remote PC updates the dual DSP program online through the network, making it easier to debug the dual DSP.

2.3 PWM signal generation and output circuit

The control platform generates PWM control signals through modulation such as SPWM and SVPWM to control the converter, and then controls the main circuit switch of IGBT and IPM modules through the drive circuit to generate AC output. On the general control platform, the 16-channel PWM signals of the event managers EVA and EVB in TMS320F2812 are introduced into the CPLD EPMl270T144, and after being processed by the CPLD and driven by SN75451 , they are output through the optical fiber HFBRl521. The PWM of the general control platform and the drive module of the main circuit are isolated by optical fiber, which can effectively eliminate the interference of the main circuit on the control platform. At the same time, the driver board receives the 16-channel fault signals sent by the driver board through the 16-channel optical fiber receiver HFBR252l and sends them to the CPLD for blocking the PWM output. Figure 4 is a single-channel optical fiber transceiver circuit.

CPLD reshapes the 16-channel PWM signals output by TMS320F2812, including adding complementary pulses, adding dead zones, limiting the minimum pulse width, etc.; blocking pulses, completing protection actions and outputting fault signals according to actual requirements. The PWM signal output by CPLD is connected to a pull-down resistor, so that when the CPLD outputs high impedance, the PWM output is a certain low level, avoiding the switch device from being mis-turned on due to the uncertain state of the PWM signal during reset or when the CPLD has no loaded program.

2.4 Switch state input and output circuit

The control platform reads the on/off status of the main circuit air switch, circuit breaker, button, etc. through the input of the switch state quantity; the main circuit circuit breaker, exhaust fan control switch, etc. are controlled through the switch state output and the on/off control output relay. The input and output of the switch quantity are composed of data, address bus, 74LVC245, optocoupler TLP52l and relay , etc. The input of the switch quantity is converted to 3.3 V level through 74LV-C244 and sent to TMS320F2812; the switch quantity is output through 74LVC244 to control the signal light and relay , etc., so as to realize the functions of debugging, indication, protection action, etc. In this design, the switch state quantity has a total of 8 input and output channels, which are all isolated by optocouplers and powered by 24 V separately. Optocoupler isolation and separate power supply can effectively isolate the main circuit and the control platform, thereby reducing the interference of the main circuit to the control platform.

2.5 Communication module and human-machine interface (HMI)

When the high-power converter is working, the control platform exchanges data with other systems such as the human-machine interface and the host computer through the communication circuit. The communication circuit is controlled by FPGA. In order to enable the dual DSP to update the program online and facilitate debugging, an FPGA EP2C20Q240 and a network controller RTL8019 are used to expand Ethernet. The FPGA needs to expand an SDRAM HY57V641620 and a FlashE28F640 to store the soft-core Nios II and μCLinux operating system that need to be loaded when the FPGA is running. In order to achieve a good human-machine interface (HMI), the general control platform also expands an LCD and keyboard input circuit. The keyboard input circuit is controlled by ZLG7290 and communicates with the FPGA through the I2C bus; ICD is a parallel interface, and its data line is multiplexed with the network card controller RTL8019, and the control signal is sent directly by the FPGA.

3. Control system software design

The control system software design mainly includes initialization, communication, MD sampling, control algorithm, SPWM modulation, fault detection and processing, etc. Figure 5 shows the main program flow.

4 Conclusion

The high-power converter universal control platform was applied to a 400 kVA shore power supply prototype, and a motor drag experiment based on SVPWM was carried out. The motor ran stably without motor vibration caused by harmonics; the voltage and current sampling data of each circuit of the main circuit were basically the same as the test results of the on-site instrument; the protection circuit could operate normally; the communication function was normal, and the dual DSP online update program was realized. It should be noted that this design is a universal control platform with complete peripheral functions. In actual products, modular tailoring is required according to relevant requirements. Compared with traditional high-power converter dedicated controllers, this universal control platform has strong computing power, large data storage capacity, can perform fixed-point and floating-point operations at the same time, has accurate and reliable analog circuits, rich communication resources and strong anti-interference ability.