Implementation of Active Power Factor Correction Circuit Based on BCM

The topology and working mode of the rectifier circuit are analyzed, the selection basis of the key parameters of the rectifier circuit is discussed, and the design method of the critical conduction mode (BCM) power factor correction Boost switch converter is proposed. The simulation results show that the designed critical conduction mode active power factor correction (APFC) circuit with MC33262 as the core can output a stable 400 V DC voltage in a wide voltage input range of 90 to 270 V, and make the power factor reach 0.99. The system performance is excellent and meets the design requirements.

Keywords: Active Power Factor Correction (APFC); Boost Converter; Boundary Conduction Mode (BCM); MC33262

1 Introduction

Active power factor correction (APFC) is an important way to use electric energy efficiently and with low pollution. It adds a power conversion circuit between the bridge rectifier and the output capacitor filter to make the power factor close to 1. The active power factor correction circuit works in a high-frequency switching state and has the characteristics of small size, light weight, and high efficiency. It has become a new hot spot in the research of power electronics technology.

2 Comparison of APFC working modes

The active power factor correction (APFC) circuit can be divided into three operating modes: continuous conduction mode (CCM), discontinuous conduction mode (DCM) and boundary conduction mode (BCM) according to whether the inductor current is continuous. The characteristics of these three operating modes are shown in Table 1. The APFC circuit design in this paper adopts the BCM working mode.

3 Working principle of BCM power factor correction (PFC) circuit

Figure 1 is a schematic diagram of a boost PFC circuit implemented in a critical conduction control mode and its control waveform and inductor current waveform in half a power frequency cycle. Figure 1(a) is a circuit schematic diagram for implementing a variable frequency control scheme, in which the error amplifier compares the feedback signal of the output voltage with the 2.5 V reference signal and amplifies it. The generated output signal and the AC input voltage detection signal are input into the analog multiplier. The analog multiplier generates a half-sine wave output signal with the same frequency and phase as the input voltage. When the power tube is turned on, the resistor R4 detects the inductor current. When the inductor current reaches the output of the analog multiplier, the current comparison detector outputs a control pulse, triggering the RS control logic part to turn off the power tube and the inductor starts to discharge, thus ensuring that the peak envelope of the inductor current is a half-sine wave with the same frequency and phase as the input voltage. When the inductor is discharged, the secondary output of the inductor is used to detect the zero crossing of the inductor current. When the inductor discharges, the RS control logic part immediately turns the power tube back on. The overall circuit adopts voltage-current dual-loop feedback control and utilizes frequency conversion control method to realize Boost type PFC circuit, and the power factor is close to 1.

4 Implementation of BCM PFC Circuit

The BCM Boost PFC circuit adopts variable frequency control, with few peripheral devices in the integrated control circuit, small size and light weight, and is suitable for low-power switching power supplies . Here, the control device MC33262 is the core, and the circuit schematic diagram is shown in Figure 2. The main circuit adopts a Boost circuit, and the control circuit is mainly composed of the MC33262 device, startup circuit, auxiliary power supply , current detection circuit, voltage detection circuit, etc.

4.1 Circuit Working Principle

The circuit adopts a dual-loop feedback control scheme. The function of the inner loop feedback is to sample the half-wave voltage output by the full-wave rectifier through the resistor divider composed of R2 and R4 and input it to the 3-pin of MC33262 to ensure that the current through the primary side of the inductor booster tracks the trajectory of the input voltage changing according to the sinusoidal law. The outer loop is used as the feedback control of the DC voltage output by the APFC converter. The DC output voltage is sampled and input to the 1-pin of MC33262 through the resistor divider composed of R5 and R7. MC33262 outputs a PWM drive signal to adjust the duty cycle of the power tube VQ1 to stabilize the output voltage. When the AC input voltage changes from 0 V to the peak value according to the sinusoidal law. The output of the multiplier controls the threshold of the current sensing comparator, forcing the peak current through the power tube VQ1 to track the change trajectory of the AC input voltage.

4.2 Circuit Design

According to the circuit principle shown in Figure 2, the circuit technical indicators are as follows: maximum output power Pn is 150 W, input voltage range: 90 ~ 270 V, output voltage Uo is 400 V, input grid frequency fac is 50 Hz, converter efficiency η is 90%, minimum switching frequency fmin is 25 kHz, output voltage maximum ripple peak-to-peak value UOP-P is 8 V, and output overvoltage protection point Uovp is 440 V.

4.2.1 Switching frequency design

The expression of switching frequency in half power frequency cycle is:

The switching frequency f(t) varies with time within the power frequency cycle of a given input voltage. The lower the power, the higher the switching frequency. Theoretically, under light load conditions, the switching frequency can reach several megahertz, but the higher the frequency, the greater the switching loss. Therefore, some critical conduction mode control devices have a maximum switching frequency limitation. The maximum frequency of MC33262 is about 400 kHz.

4.2.2 Inductor Design

The design of the inductor must ensure that the circuit operates in BCM throughout the entire operating range. Therefore, the main inductor expression can be derived as:

Theoretically, if the minimum switching frequency is given, the maximum value of the main inductance will be generated when the output power is minimum and the input voltage is maximum. A smaller minimum switching frequency of a given PFC circuit can reduce switching losses, while a larger minimum switching frequency can reduce the volume of the inductor. Most designs use 25 kHz as the preferred frequency. The voltage design index range here is 90 to 270 V. When the input voltage Uin is 270 V, fmin is generated. Substituting it into formula (2) yields: L = 398 μH. In this design, L is 420 μH.

4.2.3 Selection of output diode

BCM solves the reverse recovery problem of diode VD. In order to reduce the loss of the switch tube, a fast recovery diode can be used. Since the operating frequency of the switching power supply is above 20 kHz, the reverse recovery time of the fast recovery diode and the ultra-fast recovery diode is reduced to the nanosecond level, which reduces the loss of the power device itself and greatly improves the power supply efficiency. This design selects IDmax = 7.9 A. Similarly, considering a certain margin, the voltage stress of the diode should be at least greater than the output overvoltage protection point of 440 V. Therefore, the diode model is FR10J, and its technical parameters are 10 A, 600 V.

4.2.4 Design of filter capacitor

In the PFC circuit, a small capacitor is usually connected to the output end of the rectifier bridge to filter out the noise caused by the ripple of the high-frequency switching inductor current. If the capacitor value is too small, it may not be able to filter out the input high-frequency noise well, but its value cannot be too large, otherwise it will cause a large input voltage offset. The maximum ripple voltage of the filter capacitor is represented by △UCin(max). In general, this value can be taken as less than 5% of the minimum input voltage peak value, so the lower limit of the input filter capacitor is:

The minimum input voltage value here is 90 V. Substituting the design index into formula (3) yields the minimum value of the input capacitor Cin = 2.59 μF. Since the output voltage of the rectifier bridge is used as the reference for current following after the resistor divider, an excessively large input capacitor will distort the reference voltage waveform, thereby distorting the input current waveform as well, resulting in a decrease in power factor and an increase in harmonics. Therefore, the capacitance value of this design is 5.6 μF, and the withstand voltage of the capacitor should be greater than the maximum peak value of the input voltage, and a certain margin should also be considered. Therefore, the circuit design Cin selects a withstand voltage value of 5.6 μF and 630 V.

4.3 Selection of control circuit components

4.3.1 Multiplier Parameter Calculation

There are two input signals of the multiplier: after full-wave rectification, the AC input voltage is detected by pin 3 of MC33262 through R2 and R4. The output of the multiplier obtains a half-sine wave signal as a reference for the input current. The maximum value of the input voltage of pin 3 is clamped at 3.2 V. To reduce power loss, the current flowing through R2 should be hundreds or less. If R4=15 kΩ, then R2=1.8 kΩ, and R2=2 kΩ is actually selected. Since the circuit works in a high-frequency switching state, it will cause high-frequency noise. In order to reduce the interference of high-frequency noise on the control circuit, a small-capacity high-frequency filter capacitor C2 with a capacity of several nF is also required to be connected in parallel at both ends of R4.

4.3.2 Design of transformer secondary winding and current limiting resistor

Transformer T is the boost inductor of the APFC pre-regulator. By calculating the number of turns of the boost inductor Lp, Np=60.9 (turns), the actual integer value Np is 61 turns, the secondary winding is Ns=6, and the value of the zero current detection resistor R6 can be determined according to its loss, which should satisfy

Substituting Uo = 400 V and n = 10 into formula (4), we get: R6 ≥ 8.4 kΩ, so R6 can be selected as 22 kΩ. 0.25 W.

4.3.3 Error Amplifier Peripheral Devices

R5 and R7 realize the output voltage sampling function, and their connection point is connected to the 1 pin of MC33262, which is the inverting terminal of the error amplifier inside the controller, and its non-inverting terminal is connected to the 2.5 V reference voltage. The maximum input bias current of the error amplifier is -0.5μA, and the current passing through R5 should be much larger than the input bias current of the error amplifier. The values ​​of R5 and R7 can also be selected based on experience. Generally speaking, the current flowing through R5 is one-tenth of the circuit load current or less, so combined with the circuit design indicators, R5=1.6 MΩ, R7=10 kΩ.

4.3.4 Startup Circuit

The starting circuit is composed of R1 and C4. The value of the starting resistor is determined according to the starting current ISTART and the starting threshold voltage Uccon, that is:

Before the auxiliary winding provides energy for the normal operation of the device, C4 must provide enough energy to power the device. C4 should meet

Substituting the relevant technical parameters into formula (6), we can get: C4 ≥ 13μF. Its withstand voltage should be greater than the maximum supply voltage of the device, so this design selects C4 as a 100μF, 50V electrolytic capacitor. In addition, in order to make the circuit work stably, a voltage control loop must be added.

5 Experimental results of BCM PFC circuit

In order to analyze the BCM PFC circuit in detail, the input voltage is extended to the full voltage range, and the simulation data and theoretical data are analyzed and compared in detail. When the effective value of the input voltage is 90 V, 120 V, 150 V, 180 V, 220 V, 240 V, and 270 V, it is assumed that the circuit has no loss and the input power is 150 W. From the simulation results, it can be seen that the simulation values ​​of the input power are 164.4W, 162.4W, 161.3W, 159.0W, 157.6W, 156.9W, and 156.3W, respectively, and the simulation values ​​of the efficiency are 92.6%, 93.7%, 94.5%, 95.8%, 96.7%, 97.2%, and 97.5%, respectively. Compare the theoretical value with the simulation value. Use MATLAB to fit these theoretical values ​​and simulation values ​​into two curves, respectively, as shown in Figure 3.

As can be seen from Figure 3(a), the difference between the simulation waveform and the theoretical analysis is that the simulation value of the input power is larger than the theoretical value in the full voltage range. This is because in the theoretical analysis, the efficiency of the circuit is assumed to be 1. In the simulation, the components of the circuit also consume energy, so the simulation value of the input power is larger than the theoretical value. In addition, when the input voltage increases, the simulation value of the input power decreases, that is, it is close to the theoretical value, and the efficiency of the circuit increases, as shown in Figure 3(b). Therefore, the larger the voltage, the closer the simulation value of the input power is to the theoretical value.

The comparison between the simulation value and the theoretical value of the output voltage ripple is shown in Figure 4. It can be seen from Figure 4 that the maximum value of the simulation is less than 4 V, which is less than the given design requirement, and the theoretical value is also less than 4 V, which fully meets the design requirements.

6 Conclusion

The circuit is designed according to the design indicators of the circuit, and simulation and experimental research are carried out. The experimental results show that the converter can stably output about 400 V DC voltage within a wide voltage input range, the input current waveform is basically consistent with the voltage waveform, the power factor reaches above 0.99, and high power factor correction is achieved, which can effectively suppress input current harmonics.