A high input resistance broadband buffer amplifier constructed by a push-pull circuit

Function of the circuit

This circuit uses a surface-connected N-channel FET and is a buffer amplifier composed of a complete push-pull circuit. It can shorten the rise and fall time and is used in circuits that require wide bandwidth, fast conversion speed, high input impedance, and low output impedance.

How the Circuit Works

TT1 and TT2 are N-channel and P-channel FETs, and their VGB and ID relationship characteristics must be the same, otherwise an offset voltage will be generated between the output and input. If this circuit is used in the feedback circuit of an OP amplifier, the offset voltage can be ignored.

The gate-source voltage of the surface-connected FET directly becomes the bias voltage between the base and emitter of the output circuit. The output circuit requires about 1.5V between the base and the base, so a FET with the same drain saturation current IBSS must be selected. The purpose of TT3 is to prevent the deviation of the FET from causing the bias current of the output stage to change. When it is required to work at a higher speed, the current should be increased as much as possible so that the output stage always works in the linear range.

Select the output transistor based on the maximum collector current and allowable power consumption. Devices with high FT and small COB should be selected.

Component Selection

Although this circuit is ideal in principle, the relationship between VGB and ID of the FET (TT1.2) used in the input stage will change the operating point if there is a deviation, so the appropriate drain saturation current must be selected and controlled .