Design Challenges of Ultra-Low Jitter Clock Synthesizers

Overview

This article provides a reference design for a low-jitter clock source for high-speed data converters, with a target of < 100fs edge-to-edge jitter at clock frequencies up to 2GHz. For a 1GHz analog output frequency, the resulting jitter signal-to-noise ratio (SNR) is: -20 × log(2 × π × f × tj) = -64dB.

Design requirements

The maximum frequency of the clock design is 2GHz, however, some VCOs (voltage-controlled oscillators) and prescalers can extend it to higher frequencies, and the range of extension of different devices is also different. The reference design, simulation test and results introduced here are only for 2GHz output frequency.

Some high-speed converters use both edges of the clock signal as internal timing. This requires a strict 50% duty cycle. In addition, the target output drive capability is 10dBm/50Ω, that is, 2VP-P differential output.

Synthesizer Design Basics

Figure 1. Traditional Phase-Locked Loop

The simplest design is the traditional phase-locked loop circuit , shown in Figure 1. As mentioned above, a strict 50% duty cycle is required. Therefore, the VCO operates at twice the target clock frequency (4GHz), and then divides by 2 to obtain the target frequency and duty cycle. Since the divider introduces jitter, it is placed in the phase-locked loop to eliminate noise.

The loop filter provides low-pass filtering of the reference noise and high-pass filtering of the VCO noise. It also determines the loop settling time. Since this is a fixed frequency application, loop settling time is not an issue; the filter bandwidth can be optimized only for noise. Narrowband filters are easier to handle reference noise, but increase the noise burden of the VCO, while wideband filters have the opposite effect.

Although we need to balance between the VCO and the reference clock, studies of both have shown that it is possible to get the best performance of both. The phase noise specification of 100fs jitter determines how low the noise will be.

Phase noise is a specification relative to the carrier frequency and is inversely proportional to the frequency deviation (dBc/Hz). The sum of all phase noise is the phase noise power, which is compared to the fundamental power. Phase noise divided by fundamental power gives jitter.

For example, suppose a 2GHz VCO has -110dBc/Hz SSB (single sideband) phase noise from 10kHz to 100kHz, with a bandwidth of 90kHz, which is 49.5dB. So, the total noise is -60.5dBc. The SSB noise power is:



So, the noise voltage rms is:



The factor 2 in the square root represents the inclusion of two single sidebands¹.

The jitter is:



Equation 3 only gives the jitter for the 10kHz to 100kHz frequency offsets; the remaining frequency offsets must also be considered to determine the total jitter.

Another way to do this is to work backwards from jitter to phase noise. So, for 100fs of jitter at 2GHz:



The SSB noise power is:



Equation 5 is equivalent to a total noise power (SSB) of -61dBc. If we assume that the phase noise is uniformly distributed from 1Hz to 10MHz, then, converted to dBc/Hz, we get the following phase noise template (Figure 2).


Figure 2. Phase noise template

Undoubtedly, jitter < 100fs at 2GHz is a very good phase noise value, especially in the range of 10kHz to 100kHz. As can be seen from the figure, the phase noise at 10kHz is about -114dBc/Hz. But few discrete² VCOs can achieve this level, and of course, integrated VCOs are also difficult to achieve this goal. UMC (Universal Microwave Corporation) VCOs can achieve this low noise level. The UMX series has a bandwidth of 500MHz to 5GHz, and its 10kHz phase noise can reach less than -112dBc/Hz. Even the worst VCO in the UMX series meets our requirements.


Figure 3. Phase noise of UMX-806-D16 corresponding to the phase noise template

Figure 3 shows the worst-case phase noise of the 4GHz VCO (UMX-806-D16) and our target phase noise template. The phase noise of this VCO is high below 20kHz, but the low-frequency offset VCO noise can be suppressed by designing the PLL filter bandwidth. Assuming nothing else is affecting the phase noise, very good phase noise specifications are achieved above 10kHz. Note that these phase noise requirements are for a 2GHz oscillator. However, Figure 3 shows the curve for a 4GHz oscillator, which requires an additional divide-by-2 to achieve a 50% duty cycle. Assuming the divide-by-2 itself does not affect the total phase noise, it will reduce the VCO phase noise by 6dB, and the entire curve will shift down by 6dB.

Note that the reference clock also contributes noise, but most of it is below the loop filter bandwidth. Figure 4 shows the Burt plot and target phase noise mask for an 80MHz crystal voltage-controlled oscillator from Crystek®. Note that the PLL frequency gain will multiply the reference clock phase noise by an equal amount. So, for an 80MHz crystal and a 2GHz output, the gain is 25. As a result, the Crystek curve will shift up by 28dB. This shift means that the reference clock phase noise is very high at 1kHz³. However, the phase noise mask assumes that the total noise power is evenly distributed within the frequency offset. Of course, this is not necessarily the case, so a constant phase noise outside 1kHz plus noise within 1kHz can still meet our jitter specification.


Figure 4. Phase noise of the reference clock

The phase noise analysis of Figure 4 also includes a Vectron oven controlled oscillator (OCXO), which has very low phase noise. Note that the OCXO tends to consume more power (on the order of watts).

Synthesizer Schematic

Figure 5 is the complete circuit schematic of the reference clock and VCO discussed earlier. The PLL uses the Fujitsu® MB15E06SR, which integrates a 4mA charge pump and a prescaler up to 3GHz. Since the PLL needs to be programmed, a very simple PIC microprocessor (PIC18F2455) with a built-in USB interface can automatically perform programming tasks. This design requires a software programming user interface, and the PIC also needs to be programmed.


Clear image (PDF, 93.8KB)
Figure 5. Clock synthesizer schematic

The divider uses the Hittite® HMC361, which can operate up to 10GHz and its phase noise has little impact on performance. However, the output swing of the divider is only 0.8VP-P, which is 2dBm at 50Ω. The design goal is 10dBm output (2VP-P), so the output of the Hittite cannot meet the requirement and needs to be boosted. On Semiconductor® or Zarlink® have similar products, but their output swing is basically the same as Hittite, or even worse. Furthermore, their noise specifications are not clearly specified.

A simple transformer can be used to increase the swing of a slow clock, but transformers that can achieve 4:1 amplification above 2GHz are not common. In addition, this approach increases the difficulty of impedance design. Another approach is to use an active amplifier. Many differential amplifiers with bandwidths > 10GHz are available, but the noise specifications of the devices need to be further determined to meet the design requirements. Another question is whether the amplifier can be placed in a PLL. The Fujitsu data sheet recommends a maximum prescaler input of 2dBm (1VP-P).

Simulation Results

ADIsimPLL (written for Analog Devices by Applied Radio Labs) can be used to analyze this circuit, and it includes several UMC VCO models. Figure 6 shows a phase noise plot for a PLL consisting of a UMC 4GHz VCO without a divider and a Crystek oscillator. Below 2kHz, the reference clock noise dominates; above 2kHz, the phase detector phase noise dominates; and above 70kHz, the VCO noise dominates.

Figure 6 includes the target noise mask (thick black line) from Figure 2. Clearly, the total noise exceeds the mask below 50kHz, which will produce 200fs of jitter. A practical simulation presents a problem in how to account for the phase noise of the phase detector. It should be equal to the noise floor of the particular device (-219dBc/Hz) multiplied by the VCO/PFD frequency, which is 4000MHz/25MHz, or 44dB, shifted by 118dB. Further verification is needed, but even with the PFD (phase detector) noise removed, the result is still unacceptable (167fs).


Figure 6. Simulation results using VCO: Phase noise at 4 GHz

Except for the PFD noise, the filter is set close to the VCO noise peak at 10 kHz. The main remaining issue is the reference clock noise, and unfortunately, the better-than-template performance above 40 kHz is not enough to eliminate this noise. Therefore, another type of oscillator is needed to meet the phase noise requirements, such as an OCXO.

The printed circuit board (PCB) of this design can accommodate three or four different XO pinouts. Figure 7 shows the simulation results using a Vectron OCXO. Even considering the phase detector noise, the final jitter is 86.5 fs. This jitter leaves some margin for the unaccounted-for divider noise (which should not have a significant negative impact) and the amplifier that may be needed.


Figure 7. Simulation results using Vectron OXCO: Phase noise at 4 GHz

in conclusion

Achieving 100fs jitter at 2GHz is more difficult than we expected. Experimental data shows that this goal can be achieved using some standard PLL circuits. The key lies in the choice of VCO and reference clock. Experimental results show that the UMX VCO has excellent phase noise performance. The remaining two challenges are: (1) choosing a reference clock with sufficiently low noise; and (2) choosing the right amplifier. Fortunately, there are many parts to choose from, and the same circuit layout can be used with different pinouts. The choice of amplifier is more difficult and requires further analysis to determine whether it can be placed in the loop and its noise effect must be considered.


¹ Considering two single sidebands, the paper includes the factor of 2 both inside and outside the square root. The total noise power is twice the SSB noise power, so the total noise voltage should be equal to the SSB noise voltage.
² Refers to individual components, not modules.
³ There is high phase noise near 1MHz, but the loop filter helps to attenuate this noise.