Design of low power full adder based on majority decision logic NOT gate

O Introduction

Addition is the most basic operation in arithmetic operations. Subtraction, multiplication, division and address calculation, which are based on addition, have been widely used in very large scale integrated circuits (VLSI). Full adder is the basic unit of binary adder, so improving the performance of full adder is one of the most important ways to improve the performance of arithmetic unit.

There are many related reports on the research of full adder structure at home and abroad. Most of the research is devoted to improving the speed of full adders and reducing their power consumption. There are many ways to design full adders. The simplest method is to use combinational gates to implement the required logic function. Another commonly used method is to use transmission gates. Since transmission gates have strong logical functions and small input capacitance, full adders implemented with transmission gates are fast and simple in structure. Full adders implemented with transmission gates are simpler than full adder circuits implemented with combinational gates. However, this circuit uses CMOS transmission gates as the basic unit instead of being designed at the tube level. Therefore, this full adder circuit has redundancy and needs to be further simplified.

In combination with the above discussion, an adder unit circuit with simpler structure and better performance is proposed. It only consists of an input capacitor and a CMOS inverter, and overcomes the power consumption problem by simplifying the circuit design.

This paper first proposes the concept and circuit design of majority decision logic gate, and then proposes a full adder circuit design based on majority decision logic gate. The three main features of this full adder are fewer transistors, working at very low power supply voltage and elimination of short circuit current. Simulation results show that this new structure can well complete the logic function of full adder.

1 Majority decision logic gate

1.1 The logical negation of majority decision

Majority Logic is defined as: if the number of logical 1s is greater than the number of logical 0s, the output is logical 1; if the number of logical 0s is greater than the number of logical 1s, the output is logical 0. CO in Table 1 is the majority logic of A, B, CI, and the logical expression is CO=M(A, B, CI). Majority-not Logic is the majority logic not function, and in Table 1 is the majority logic not function of A, B, CI, and the logical expression is F=F(A, B, CI).

1.2 Circuit Design of Majority Decision NOT Gate

Figure 1 is a three-input majority decision logic NOT gate circuit. Among them, C1=C2=C3, which is composed of input capacitors and a static CMOS inverter. The number of input terminals can be increased by simply increasing the number of input capacitors. The function of the capacitor network is to separate voltages. When the number of 0s in the input terminal is greater than the number of 1s, the output of the capacitor network is 0, and the output is a high level 1 (VDD) after the inverter; when the number of 1s in the input terminal is greater than the number of 0s, the output of the capacitor network is 1, and the output is a low level O (0 V) after the inverter. The capacitance value of the input capacitor is about 0.05 fF, which has no effect on the circuit.

Metal oxide semiconductor (MOS) capacitors can be selected as input capacitors. Compared with other capacitors, MOS capacitors have the advantages of small chip area, large capacitance, and easier matching. The chip area occupied by a MOS capacitor is equivalent to that of an ordinary transistor. Generally, for the same area, the PMOS capacitor value is greater than the NMOS capacitor value. Therefore, PMOS capacitors can be selected to implement the input capacitor of the majority decision logic NOT gate.

The power consumption of ordinary CMOS gate circuits mainly consists of three parts: dynamic power consumption Pswich, short-circuit power consumption Pshort, and static leakage current power consumption Pleak, as shown in formula (1). If formula (2) is satisfied, the two tubes cannot be turned on at the same time. If Pshort is removed, the power consumption will be significantly reduced.

In the formula: fcp represents the system clock pulse; Vim is the voltage variation range of node i (ideally VDD); CiL is the equivalent load capacitance of node i; ai is the activity factor of node i; Iisc and IL are short-circuit current and leakage current respectively; P is the total power consumption.

In the formula: VthP and VthN are the turn-on voltages of PMOS tubes and CMOS tubes respectively. The turn-on voltage refers to the voltage when the insulated gate field effect transistor (MOSFET) channel is formed.

In Figure 1, because the circuit uses only two transistors, the power supply voltage can be reduced. Relative to the power supply voltage, Pswich will decay at a quadratic rate. It only needs to satisfy equation (2) and remove Pshort. Therefore, its power consumption is much lower than that of traditional CMOS gate circuits.

Although reducing the power supply voltage can reduce power consumption, it will affect the output waveform of the circuit. Equations (3) and (4) show the effect of reducing the power supply voltage and increasing the turn-on voltage on the high-low level conversion delay time of the tube.


2 Design of full adder

2.1 Logic Design of Full Adder

According to the definition of full adder, its truth table is shown in Table 1. Among them, A and B are addend and augend, CI is the carry from the lower bit; S is the sum output, CO is the carry output. According to the previous analysis, the carry output CO of the full adder can be expressed as the majority decision logic of the input A, B, CI, and the sum output S is the majority decision logic of the five variables A, B, CI, CO1 , CO2 (where CO = CO1, = CO2). It can be expressed in logic form:

2.2 Circuit design of full adder

According to the logical equations (5) and (6), the circuit is designed as shown in Figure 2. In this design, only two majority decision logic NOT gates are used. Only 6 MOSFETs are needed to realize the optimized CMOS full adder, and transistor-level simulation is performed using PSpice. The results show that this new full adder can correctly complete the logical function of the adder. In Figure 2, C1=C2=C3=0.05 fF, 2C4=C5=C6=C7=2.88 fF.

3 Conclusion

A low-power one-bit full adder circuit design is proposed, which is realized by input capacitor and CMOS inverter only. The circuit uses only 6 transistors, thus achieving the purpose of reducing power consumption. Fewer transistors, working at very low power supply voltage and eliminating short-circuit current are the three main features of the full adder.