Low Voltage Transconductance Operational Amplifier for Sigma-Delta Modulator

Driven by the rapid growth of demand for small-size, high-performance, portable mobile communications and consumer electronics products, Sigma-Delta analog-to-digital converters have been more widely studied and used. Sigma-Delta analog-to-digital converters have the characteristics of low circuit matching accuracy and high precision. The modulator with transconductance operational amplifier OTA (Operational Transconductance Amp-lifier) ​​as the core is the analog circuit part of the Sigma-Delta analog-to-digital converter circuit. Its structural selection and circuit parameter design greatly affect the speed and accuracy achieved by the entire analog-to-digital converter.

A fully differential folded cascode transconductance operational amplifier design for a 16-bit third-order single-loop CIFB Sigma-Delta modulator is proposed here. The circuit simulation results show that the design performance indicators meet the requirements of the modulator.

1 Circuit performance requirements and structural parameters

1.1 Analysis of Transconductance Operational Amplifier Specifications

The limited gain of the op amp will cause phase shift, which will cause the zero point of the noise transfer function (NTF) to deviate from the normal position. The third-order single-loop CIFB Sigma-Delta modulator is implemented with a Butterworth third-order filter. The advantage of this structure is that it is insensitive to the coefficients and allows a large tolerance for the coefficients and zero poles. The third-order single-loop CIFB Sigma-Delta modulator is implemented with a Butterworth third-order filter. The advantage of this structure is that it is insensitive to the coefficients and allows a large tolerance for the coefficients and zero poles, so the gain requirements for the op amp are lower. Usually, the op amp gain greater than 60 dB will not affect the performance of the modulator.

The output voltage of the integrator requires a certain amount of settling time, part of which is the nonlinear conversion time tSR, which depends on the slew rate of the op amp, and the other part is the linear voltage settling time tL, which depends on the unity gain bandwidth of the op amp. In order to prevent harmonics from appearing in the output, the output of the integrator must be settled within half a clock cycle.

Figure 1 is a behavioral simulation model of a third-order single-loop modulator. According to the behavioral synthesis results of Figure 1, only when the OTA's slew rate is greater than 40 V/μs and the unity gain bandwidth is greater than 50 MHz can the requirement of equation (1) be met.

1.2 Circuit structure considerations

Transconductance operational amplifiers mainly include two-stage op amps, gain-enhanced op amps, telescopic cascodes, and folded cascodes. Among them, in the two-stage amplification structure, the sub-pole frequency is determined by the load capacitance, which makes its bandwidth small, the speed is limited, and the power consumption is large, and the power supply rejection ratio and common mode rejection ratio are poor. The telescopic cascode structure has the characteristics of good frequency characteristics and low power consumption. However, under low power supply voltage, its output swing and common mode input range are difficult to meet the expected requirements. The gain-enhanced op amp, although it has a high DC gain, has huge power consumption and is not suitable for this system design. Taking all factors into consideration, the folded cascode structure with faster speed, larger output swing, wider common mode input range and compromised performance is adopted.

2 Circuit Analysis and Design

2.1 Folded Cascode Transconductance Operational Amplifier

There are two options for the input tube of the folded cascode transconductance operational amplifier. The NMOS input pair has a higher transconductance, which can make the operational amplifier achieve a higher DC gain, but PMOS needs to be used as the cascode tube. Under the same bias conditions, the transconductance of the PMOS tube is 40% to 50% of that of the NMOS tube, which limits the sub-pole frequency of the operational amplifier. If PMOS is used as the input stage, the operational amplifier has lower noise and higher sub-pole frequency, lower noise, but smaller DC gain. Since this design does not require high DC gain. Therefore, PMOS input is used. The structure of the transconductance operational amplifier is shown in Figure 2.

VM1 and VM2 are PMOS input differential pair tubes that convert the input differential voltage into differential current, and generate output voltage after passing through VM5 and VM6. VM11 is a long-tail current sink that provides static operating current for the input differential pair tubes and improves the input common mode rejection ratio (CMRR). By analyzing the circuit with small signals, the DC gain of the folded common source and common gate op amp can be obtained.

In the formula, r0 is the small signal output resistance of the MOS tube, which is proportional to the channel length; gm is the transconductance of the MOS tube.

The dominant pole of this op amp is

When only considering the main capacitance, namely the gate-source capacitance of VM5, the secondary pole is

From formula (5), we can know that changing the circuit operating current and load capacitance can also change SR. In this design, the load capacitance CL is 5pF, considering the stability of the op amp. The phase margin PM of the op amp must be greater than 60°. Increasing the operating current will increase the DC gain and unity gain bandwidth GBW of the op amp, and at the same time increase SR, but will cause PM to decrease and the circuit power consumption to increase. Therefore, the operating current of the op amp should be considered in a compromise.

2.2 Common-mode feedback circuit

The feedback loop of the op amp in a fully differential op amp only provides differential-mode voltage but not common-mode voltage. A common-mode feedback circuit (CMFB) is required to stabilize the common-mode voltage of the differential output signal. This circuit is shown in Figure 3.

Sl and S2 are two-phase non-overlapping clock signals. Vout is the output voltage signal of the op amp. Vcm is the expected value of the common-mode output voltage of the op amp, which is the input signal here. Vb4 is the adjustment voltage of the common-mode feedback circuit, which is connected to the gates of op amps VM3 and VM4. Vb4 and Vout form negative feedback in the op amp. Vbais is the expected voltage value of Vb4. When clock S1 is working, S2 is disconnected, and C1 is charged, and the charge is Q1=2C1(cm／Vbais). At the same time, the total charge across capacitor C2 is Q2=C2(Vout+ +Vout- -2Vb4). When clock S2 is working, C1 and C2 are connected in parallel. At this time, the total charge of the capacitor in the circuit is:

According to the law of conservation of charge, Q1+Q2=Q3, that is:

If the actual common-mode voltage output by the op amp is greater than the ideal value Vcm, Vb4 increases and Vout decreases; if the actual common-mode voltage output by the op amp is less than the ideal value, Vb4 decreases and Vout increases. The common-mode feedback circuit achieves the stability of the common-mode output voltage of the op amp by using negative feedback by changing the gate voltage of the op amp. According to formula (6), C1 and C2 are 0.1 pF and 0.4 pF respectively.

3 Simulation results and analysis

A fully differential folded cascode transconductance operational amplifier was designed based on SMIC 0.18μm PDK, and the layout design was completed, as shown in Figure 4.

The op amp is simulated and analyzed by Spectre. Under the conditions of operating temperature of 27°C, operating voltage of 1.8V, and load capacitance of 5pF, the amplitude-frequency characteristic curve is shown in Figure 5. The DC gain is 72dB, the unity gain bandwidth is 91.06MHz, the phase margin is 83.4°, and the circuit reaches a stable state.

Table 1 compares the performance of the literature, literature and this design using the same circuit structure. It can be seen that this design has good comprehensive performance.

4 Conclusion

A fully differential folded cascode transconductance operational amplifier for Sigma-Delta modulator is designed based on SIMC 0.18μm CMOS mixed-signal process. By optimizing the circuit parameters, it achieves good comprehensive performance in a low-voltage power supply environment of 1.8 V without increasing the complexity of the circuit, which fully meets the practical application needs of Sigma-Delta modulator.