Principle and Application of TLV2544/2548 Multi-channel 12-bit Serial A/D Converter

1 Overview

TLV2544/2548 is a group of high-performance 12-bit low-power/high-speed (3.6μs) CMOS analog-to-digital converters produced by TI. It has high precision, small size, multiple channels, flexible use, and sample-and-hold function. The power supply voltage is 2.7V~5.5V. In addition, TLV2544/2548 has 3 input terminals and a three-state output terminal, which can provide a 4-wire interface for the most popular microprocessor serial port (SPI). When connected to a DSP, a frame synchronization signal (FS) can be used to indicate the beginning of a serial data frame. In addition to high-speed analog-to-digital converters and multiple control functions, the device also has an on-chip analog multiplexer that can select multiple analog voltages or any of the three internal self-test voltages as input. The power consumption of TLV2544/2548 is very low when working, and the software/hardware/automatic shutdown mode and programmable conversion speed further enhance its low power consumption characteristics. It also has a built-in conversion clock (OSC) and voltage reference, and can use an external SCLK as the conversion clock source to obtain a higher conversion speed (up to 3.6μs at 20MHz SCLK). There are two different internal reference voltages to choose from. Figures 1 and 2 are the functional block diagram and pin arrangement of TLV2544/2548, respectively, and Table 1 is its pin description.

Table 1 Pin Description

Table 2 TLV2544/TLV2548 Configuration Register (CFR) Bit Definition

*These bits are only valid in 10 and 11 conversion modes

The internal functional structure of the two chips TLV2544/2548 is the same, the difference is that the former has 4 analog input channels, while the latter has 8. The following takes TLV2544 as an example for introduction.

2 Working Principle

The TLV2544 has 4 analog inputs and 3 internal test inputs, which can be selected by the analog multiplexer according to the input command. The input multiplexer adopts the break-before-make type because this can reduce the input noise caused by channel switching.

There are two modes for starting the working cycle of TLV2544: one is when FS is not used (FS=1 at the falling edge of CS), the falling edge of CS is the start of the cycle. At this time, the input data is shifted in at the rising edge of SCLK, and the output data changes at the falling edge. Although this mode can also be used for DSP, it is generally used in SPI microcontrollers. The other is when FS is used (FS is a valid signal from DSP), the falling edge of FS is the start of the cycle, and the input data is shifted in at the falling edge of SCLK, and the output data changes at its rising edge. This mode is generally used for TMS320 series DSPs.

TLV2544 has a 4-bit command set (stored in the command register CMR) and a 12-bit configuration data field. Most commands only require the first 4 MSBs, that is, the lower 12 bits of data are not required. It is worth noting that when the device is powered on and initialized, it is first necessary to write the initialization command A000h into the CFR configuration register, and then program the device. The programming method is to write the programming data in the lower 12 bits 000h of the initialization command A000h to specify the working mode of the device. The programming definition is listed in Table 2, and the programming information is retained in the power-off state of H/W or S/W. When the device is programmed, the microprocessor sends a 16-bit serial data to write to CFR. If the SCLK is interrupted after the first 8 bits are input, the remaining 8 bits are input after SCLK is restored. A read CFR command can read the status of CFR to verify whether the write control command is correct. Other control commands can be found in Table 3.

Table 3 TLV2544/TLV2548 command set

If the first 4 bits of input data are decoded as one of the conversion commands, the sampling cycle begins. There are generally two sampling modes: normal sampling and extended sampling. Normal sampling actually uses software to start the A/D conversion mode. When the A/D converter is sampling normally, the sampling cycle is programmable, which can be 12SCLKs (short cycle sampling) or 24SCLKs (long cycle sampling). When SCLK is higher than 10MHz or the input source resistance is high, long cycle sampling can make the sampled input analog signal reach 0.5LSB accuracy. If normal sampling cannot achieve the required A/D conversion accuracy, extended sampling should be used. Extended sampling uses hardware to start the A/D conversion. After a negative pulse signal with a width greater than 800ns is input to the pin CSTART, the A/D conversion begins. The falling edge of CSTART is the beginning of the sampling cycle, and the rising edge of CSTART is the end of the sampling cycle and the beginning of the conversion.

3 TLV2544 conversion mode

The TLV2544 has four conversion modes: single mode, repetitive mode, scan mode, and repetitive scan mode. Available modes 00, 01, 10, and 11 are used. Each mode works slightly differently, depending on how the converter samples and which interface is used. The trigger signal for the conversion can be a valid CSTART (extended sampling), CS (normal sampling, SPI interface), or FS (normal sampling, TMS320 series DSP interface) mode. When FS is used as a trigger signal, CS can be protected to be valid all the time without jumping through the trigger sequence. Different types of trigger signals should not be mixed in repetitive mode and scan mode. When CSTART is used as a trigger signal, the conversion starts on the rising edge of CSTART. If a valid CS or FS is used as a trigger signal, the conversion will start on the 16th or 28th SCLK edge.

The working timing of TLV2544/2548 is divided into two categories: conversion and no conversion. No conversion cycles are read and write cycles (configuration), and these cycles do not perform conversions. The conversion cycle has four conversion mode cycles. Figures 3 and 4 respectively show the timing diagrams of the CFR write cycle (FS=1) and single extended sampling in mode 00 of TLV2544/2548 (using FS signal, FS pin connected to TMS320 series DSP).

In addition, the TLV2544/2548 has a built-in reference whose level can be programmed to 2V or 4V. If the internal reference is used, REFP is set to 2V/4V and REFM is set to 0V. If the reference source is programmed to be external, an external reference can also be used through the two reference input pins REFP and REFM. The maximum or minimum value of the analog input, external reference should not exceed the positive power supply or be lower than GND. When the positive input signal is equal to or higher than REFP, the digital input is full scale, and when the input signal is equal to or lower than REFM, it is zero.

Device power-up and initialization requires that the processor type be determined by writing A000h to the TLV2544/2548 and then programming the device. The first conversion after the device is powered on or after recovering from power-down mode is invalid.

4 Applications

The fastest and most effective way to transmit data between TLV2544 and microprocessor is to use serial peripheral interface (SPI), but this requires the microprocessor to have SPI interface capability. For microprocessors without SPI or similar interface capability, software synthesis SPI operation is required to connect with TLV2544. Figure 5 shows the interface circuit between TLV2544 and microcontroller AT89C2051. Because it is connected to the microprocessor, the FS terminal (connected to high level) is not used. The circuit uses internal reference, and two decoupling capacitors of 0.1μF and 10μF are connected between REFP and REFM. The SDI, SCLK, EOC/INT, and CS terminals of TLV2544 are provided by P1.3, P1.4, P1.5, and P1.6 in the bidirectional I/O port of the microcontroller. The output (SDO) data of the conversion result is received by P1.2 of port 1. The circuit uses extended sampling mode, CSTART terminal is connected to P1.7, and sampling and conversion are controlled by hardware. Its interface software consists of a main program and a subroutine. The main program first initializes the P1 port, and then programs the TLV2544 to determine the working mode. The subroutine "SPI-IO" is used to simulate the I/O operation of the SPI. The SPI function is implemented by using the accumulator A and the left circular shift instruction (RLC) with carry to simulate the operation of the SPI shift register. The program is as follows:

ORG 0000H

AJMP START

ORG 0030H

START: MOV P1, #0FFH

MOV P3, #0FFH

CLR EA

CLR ET1

CLR P1.4

SETB P1.6

CONFIG: MOV R1, #0A0H

ACALL SPI_IO

MOV R1, #00H

ACALL SPI_IO

SETB P1.6

MOV R1, #10101000B;

ACALL SPI_IO

MOV R1, #00000000B

ACALL SPI_IO

SETB P1.6

S/R: MOV R1, #ACALL SPI_IO

RESULT

MOV R1, #00H

ACALL SPI_IO

MOC R3，A；LOW BYTE RESULT

SETB P1.6

NOP

CLR P1.7/CSTART LOW，START SAMPLING

MOV R6, #08H

DELAY: NOP

NOP

NOP

DJNZ R6, DELAY

SETB P1.7;

JB P1.5, $;/INT

SETB P1.6

Processing of conversion results

AJMP S/R

SPI_IO;CLR P1.6

CLR P1.4

MOV R0, #08H

MOV A, R1

SPI_IO1: MOV C, P1.2

RLC A

MOV P1.3,C

SETB P1.4

CLR P1.4

DJNZ R0,SPI_IO1

RET