Study on the Mismatch Effect and Elimination Method in Differential Amplifier

With the development of microelectronics manufacturing, it is urgent to make high-speed and highly integrated CMOS circuits, which has prompted the process level of analog integrated circuits to reach the deep submicron level. Because channel length, channel width, threshold voltage and substrate doping concentration do not change proportionally with the reduction of device size, the mismatch of devices becomes more obvious as the device size decreases. In short-channel CMOS circuits, the characteristic changes caused by mismatch may limit the reduction of device size and affect the development of process level, so the elimination of mismatch becomes more important.

1 Differential Amplifier Performance

The purpose of a differential amplifier is to suppress the common-mode output and increase the differential-mode output. It is expected that the differential-mode output voltage changes proportionally with the change of the differential-mode input voltage. The common-mode input portion of any signal must be suppressed in the circuit. In an ideally symmetrical differential amplifier, the output value of each side is equal to the output value of the other side. When Vi1=-Vi2, Vo1=-Vo2, and the amplifier is ideally symmetrical. In other words, when the input is an ideal differential-mode voltage (Vic=0), the output is also a pure differential-mode voltage (Voc=0), so Adm-cm=0. Similarly, when only the common-mode voltage (Vid=0) is input, Acm-dm=0. However, even in an ideally symmetrical differential amplifier, it is impossible to achieve Acm=0. Moreover, even devices with the same nominal value will have limited mismatches (mismatches) due to manufacturing process reasons. Therefore, non-ideal differential amplifiers themselves still have mismatches.

An important aspect of differential amplifier performance is the minimum DC and AC differential voltages that can be detected. The mismatch effects and temperature drift of the amplifier both produce indistinguishable DC differential voltages at the output. Similarly, mismatch effects and temperature drift can increase the non-zero common-mode input-differential-mode output gain. Non-zero Acm-dm is particularly important for amplifiers because it converts the common-mode input voltage to a differential-mode output voltage, but it is treated as a differential-mode voltage signal at the input of the next stage.

As shown in Figure 1, when Vin=0 and completely symmetrical, Vout=0, but in the presence of mismatch, Vout≠0. For differential amplifiers, the impact of mismatch effects on DC performance is mainly in two aspects: input offset voltage and input offset current. These two parameters describe some input reference effects of DC performance in differential amplifiers. As shown in Figure 2, the DC characteristics of a matched amplifier are exactly the same as the DC characteristics of an ideal amplifier when an offset voltage source is connected in series at the input and an offset current source is connected in parallel at the input. Only when these two parameters exist, the offset model is correct.

2 Process to eliminate mismatch

The characteristics of a MOS tube in the saturation region are expressed as: 1/2μCoxW/L(VGS-VTH)2. For two nominally identical transistors, the mismatch between μ,Cox, W, L and VTH results in a mismatch in drain current (VGS is fixed) or a mismatch in gate-source voltage (drain current is fixed). Intuitively, it can be assumed that as W and L increase, their relative mismatches, △W/W and △L/L, respectively, decrease, that is, larger devices exhibit smaller mismatches. A more important observation is that as the area of ​​the transistor (W/L) increases, all mismatches decrease. For example, increasing W will reduce both △W/W and △L/L. This is because as WL increases, random changes undergo a greater "averaging" process, so their amplitude decreases. For the case shown in Figure 3, △L2<△L1. This is because if the device is viewed as a parallel connection of many small transistors, as shown in Figure 3, if each width is W0, then the equivalent length can be obtained as:

Where: △L0 is the statistical value of the length variation of a transistor with a width of W0. The equation shows that for a given W0, as n increases, the variation of Leq decreases, as shown in Figure 4.

The above conclusions can also be extended to other device parameters. For example, assuming that the device area increases, μCox and VTH have a smaller mismatch. As shown in Figure 5, the reason is that large-size transistors can be decomposed into series and parallel connections of small unit transistors with width and length of W0 and L0 respectively. Among them, each unit presents (μCox)j and VTHj. For a given W0 and L0, μCox and VTH undergo a larger averaging process, resulting in a smaller mismatch between large-size transistors.

3 Layout Methods to Reduce Mismatch

Although some mismatch is inevitable in circuit design, especially in fully differential circuits, due to circuit mismatch, the symmetry of the device can be used to optimize the transistors in the layout design, and the symmetry of the device and the surrounding environment can be designed to minimize the mismatch caused by the process manufacturing principle.

As shown in Figure 6(a), if two MOS tubes are placed in different ways as shown in Figure 6(b), a large mismatch will occur due to the different characteristics along different axes in many steps of photolithography and wafer processing. Therefore, the solutions of Figures 6(c) and (d) are more reasonable. The choice of these two is determined by a subtle effect called "gate shadow".

As shown in Figure 7(b), in order to avoid the channel effect, the injection direction (or wafer direction) is usually tilted by about 7° during source-drain ion injection, so that the gate polysilicon will block some ions and form a shadow area. As a result, there is a narrow area in the source or drain area, which receives less injection, so after injection annealing, the diffusion of the source and drain edges produces a slight asymmetry.

FIG7(a) shows the structure when the gate shadow exists. In the figure, if the shadow area appears in the source area (or drain area), the two devices will not be asymmetric due to the shadow. In the figure, even if the source (or drain) of the two tubes in the shadow area is marked, the two MOS tubes are different. This is because the right side of the source area of ​​the M1 tube is the M2 tube, and the right side of the source area of ​​the M2 tube is the field oxide. Similarly, the structures on the left side of M1 and M2 are also different. That is to say, in the manufacturing process, the process steps around M1 and M2 are inconsistent. Therefore, the structure shown in FIG8 is better.

The inherent asymmetry of the structure shown in FIG8 can be improved by adding two dummy MOS transistors on both sides of the transistor, because this can make the environment around the M1 and M2 transistors almost the same, as shown in FIG9.

At the same time, it is also important to maintain the same environment on both sides of the symmetry axis. For example, in the layout, there is only one MOS tube with an irrelevant metal line passing through it, which will reduce the symmetry and increase the mismatch between M1 and M2. In this case, you can also place an identical metal line on the other side (see Figure 10). The best way is to remove the metal line that causes asymmetry.

Symmetry becomes more difficult for large transistors. For example, in the differential pair shown in Figure 11, the width of both transistors is relatively large to keep the input offset voltage small, but the gradient along the x-axis will cause a significant mismatch. To reduce the mismatch, a "co-center" layout method can be used. In this way, the first-order gradient effects along the x-axis and y-axis will cancel each other out. As shown in Figure 12, this layout divides both M1 and M2 into two transistors with a width of 50% of the original, placed diagonally and connected in parallel. However, routing on the layout is difficult, often resulting in system asymmetry as shown in Figure 13, or overall asymmetry caused by differences in line-to-ground capacitance and line-to-line capacitance. For larger circuits, such as op amps, routing may be too complex to be implemented.

The linear gradient effect can also be suppressed by "one-dimensional" cross-coupling as shown in Figure 12. Here, all four transistors with a width of 50% are arranged in a row, and M1 and M2 can be composed of two adjacent transistors connected to the two farthest transistors, or two groups of spaced transistors connected.

To analyze the gradient effect in this structure, assume that the gate oxide capacitance change between every two adjacent half-width transistors is △Cox. Connect M1a and M4a in parallel, and we get:

Therefore, this type of cross-coupling cancels out the influence of the gradient effect. If the combination shown in Figure 13 is used, we get:

Equations (4) and (5) show that the method shown in FIG13 has poor error elimination capability.

4 Conclusion

Aiming at the mismatch of CMOS differential amplifier transistors, the causes of the mismatch are analyzed theoretically, and the circuit design method and layout design method are introduced to eliminate the offset voltage. The proposed circuit technology is simulated and verified to achieve the effect of reducing the offset voltage.