Advantages of Serial RapidIO Switches

Advantages of Serial RapidIO Switches

EMIF6? is a proprietary interface developed by Texas Instruments that has been used in the industry for many years with good reviews. However, EMIF6? is now being used in applications where it has never been tried before, such as DSP-to-DSP connections. This article describes the advantages and disadvantages of an eight-port EMIF6? switch using an FPGA compared to a Serial RapidIO switch running at the same effective bandwidth.

The EMIF standard is a mature, stable parallel external memory interface that has proven to be beneficial in many applications. However, its capabilities are limited to the host and require expensive CPU interrupt service routines to transfer data from other hosts in the system to the device. Supporting the EMIF interface may also require significant software overhead (depending on the size and frequency of data transfers). Figure 1 shows an example of a traditional EMIF application, with transfers from a CR ASIC to a DSP via a CPU interrupt + EDMA method.

By choosing an advanced serial interface such as Serial RapidIO, a number of general advantages can be achieved:
* Configurability and performance – RapidIO supports each link at 1.25, 2.5 and 3.125Gb rates and can support up to eight 4x links or sixteen 1x links. It is deterministic and low latency and provides a non-blocking switch matrix architecture.
* Control – RapidIO features configurable CPU interrupt control, support for error management, and support for congestion control through performance monitoring statistics. It also provides CRC processing for hardware error recovery.
* Software support – The inclusion of hardware termination endpoints allows for lower software overhead. In addition, RapidIO requires only a low level of configuration and functional support while providing a highly abstracted information passing API. It also has the advantage that the CPU overhead does not need to be determined by the size of the data being transferred (for example, through a small number of control messages).

Figure 2 shows the same application as Figure 1, but implemented using Serial RapidIO. The specific advantages of taking this approach over EMIF6? can be summarized as follows:
* Flexibility – EMIF6? limitations include that it is not an open standard interface and its bandwidth is limited to 8Gb/s half-duplex. In addition, it is not a scalable solution. In contrast, Serial RapidIO has an open standard interface, scalable bandwidth up to 20Gb/s, and a scalable architecture.
* Performance – EMIF6? is a lossy system that does not store and forward or provide data prioritization. In addition, there is undetermined latency through the switch. Serial RapidIO is a lossless system that guarantees packet delivery with four priority levels. There is deterministic latency through the switch.
* Development Cost – When using the EMIF6? interface, FPGA design and validation resources are required. The test bench costs that must be incurred cannot be underestimated, and finally, ongoing product support is required. However, with Serial RapidIO, no silicon design is required and the solution is less expensive to implement due to the higher relative I/O requirements of EMIF64. At the same time, the PCB complexity is reduced – a single 64-bit EMIF interface requires approximately 97 pins, meaning that an eight-port switch requires only 776 interface pins – thus reducing costs.
* Other advantages – Serial RapidIO provides CRC processing for hardware-based error recovery, while EMIF64 has no error detection/correction. In addition, the latter does not provide status or confirmation feedback, while Serial RapidIO provides error management and reporting capabilities. In addition, the wider parallel interface takes up more PCB space than the serial interface.

One thing that is essentially the same for both solutions is the power requirements. Endpoint power consumption is roughly the same for both when using equal bandwidth configurations. EMIF has a half-duplex bandwidth of 8Gb/s when running at 133MHz in 64-bit mode. Serial RapidIO has a full-duplex bandwidth of 4Gb/s when running at 1.25Gb/s in x4 mode. Although switch power consumption depends on how the FPGA is implemented and the functions included, the power consumption is roughly the same.

Figure 3 shows a component diagram of the Tundra Tsi578 Serial RapidIO switch, which is an 80Gb/s full-duplex Serial RapidIO switch that complies with the open standard and version 1.3 (latest version) of the Serial RapidIO Interconnect Specification. A highly scalable solution for mesh, matrix architectures and integrated systems, the Tsi578 provides designers and architects with configuration options to match the exact I/O bandwidth requirements of a variety of network, wireless and video infrastructure applications. It can be configured with up to eight 4x links or up to sixteen 1x links, and each 4x link can be broken down into two 1x links. The switch supports 1.25, 2.5 and 3.125Gb rates, and each port can be configured for 1.25, 2.5 or 3.125Gb/s. The ports are completely independent, and the switch supports mixed speed and bandwidth configurations.

Ease-of-use features include "hot swap" - inserting or removing field-replaceable units under power. In terms of general performance, the switch achieves low latency with packet cut-through, provides full-duplex operation for line-speed termination and non-blocking switch matrix architecture, and prevents congestion in the line backbone. It also has integrated programmable XAUI SerDes capabilities. Tsi578 uses 0.13um CMOS technology and a 27mmx27mm size and 675-ball FCBGA package, which is backward compatible with its predecessor Tsi568A.

The third generation Tsi578 switch uses innovative switch matrix architecture management to improve data throughput for next generation communication infrastructure platforms, including ATCA and MicroATCA applications. This switch can send packets to more than 6,000 endpoints and has independent unicast and multicast routing mechanisms and error management extensions, which are very helpful for these platforms.

Multicast routing can simultaneously interconnect Serial RapidIO-enabled processors and peripherals at an aggregate bandwidth of 80 Gb/s. In addition, extensive non-blocking fabric management features include fabric monitoring to monitor and manage traffic, error management to provide proactive notification of problems to the fabric controller, programmable buffer depth to guarantee bandwidth, and independent unicast and multicast routing mechanisms. Traffic throughput is improved through significantly better throughput, enhanced performance monitoring statistics, and advanced scheduling algorithms.

The Tsi578's port configuration is extremely flexible, while using low-power, high-speed SerDes to easily optimize power consumption. To help simplify signal channel routing, the switch also supports I/O channel switching. The device requires 1.2V and 3.3V power rails and can operate within industrial and commercial rated temperature ranges. The switch also supports the ACGA version of the IEEE 1149.6 JTAG standard for high-speed interconnects.

in conclusion

The combination of the Tundra Tsi578 switch and the Texas Instruments TMS320C6455 provides the highest system-level performance for any application using a DSP cluster. Moving from a traditional DSP EMIF to a Serial RapidIO switch approach enables a powerful, feature-rich design that scales to multiple DSP densities. Serial RapidIO switches cost less than half the cost of FPGA EMIF64 switches and require far fewer development resources.

Using hardware to terminate Serial RapidIO endpoints significantly reduces DSP software support. Ultimately, the cumulative savings in MIPS across the DSP cluster improves overall system performance and value.