Low power consumption 6-transistor SRAM unit design

introduction

　　In the traditional 6T-SRAM structure, the data storage node is directly connected to the bit line through the access tube. In this way, during the reading process, the storage node data will be disturbed due to the voltage division between the access tube and the pull-down tube. In addition, due to this direct read/write mechanism, the storage node is easily affected by external noise, which may cause logic errors.

　　In addition to data stability issues, the increasing chip leakage current is another issue that needs to be considered. In modern high-performance microprocessors, more than 40% of power consumption is caused by leakage current. As more and more transistors are integrated into microprocessors, the problem of leakage power consumption will become more prominent. In addition, leakage is the only source of energy consumption in standby mode, and SRAM cells are an important source of leakage current.

　　Based on the analysis of traditional 6T-SRAM and the above considerations, this paper proposes a new 6-transistor SRAM unit with high reliability and low power consumption. Due to the conflict between read current and noise margin, this structure adopts a read/write separation mechanism to separate the storage node and the read output, so that the fluctuation of the bit line will not interfere with the value of the storage node; in addition, only one bit line is required to work in each read or write process, so the power consumption is reduced in comparison. The simulation results show that the read/write speed of this structure is almost the same as that of the ordinary 6-transistor SRAM.

　　1 Introduction to 6T-SRAM Storage Cell

　　The structure of the 6-tube storage unit is shown in Figure 1.

　　1.1 6-tube unit structure and working principle

　　The transistor-level circuit of the 6T-SRAM cell structure is shown in Figure 1. It consists of 6 tubes, and the entire unit is symmetrical. Among them, M1~M4 constitute a bistable circuit to latch a 1-bit digital signal. M5 and M6 are transmission tubes, which complete the function of connecting or disconnecting the storage unit with the peripheral circuit when performing read/write operations on the memory. Access to the unit is enabled through the word line WL (Word Line). When the word line WL is at a high level, the transmission tube is turned on, so that the content of the storage unit is transmitted to the bit line BL (Bit Line), and the inverse signal of the unit information is transmitted to the bit line

, the peripheral circuits are connected through BL and

During the write operation, the peripheral circuit of the SRAM cell array transmits voltage to BL and

As input, after the word line WL is enabled, information is written into the memory cell.

　　1.2 Static Noise Margin SNM

　　Static noise margin SNM is an important parameter to measure the anti-interference ability of storage cells. It is defined as the maximum DC noise amplitude that the storage cell can withstand. If this value is exceeded, the state of the storage node will be incorrectly flipped. With the continuous development of digital circuits, the power supply voltage VDD gradually decreases, and the external noise becomes relatively large. As shown in Figure 1, the 6T-SRAM has a path from the storage node to the bit line BL in the read operation. When the access tube is turned on, BL and the storage node are directly connected. Therefore, external noise can easily destroy data, and the noise margin is unprecedentedly challenged.

　　2 Introduction to the new 6T-SRAM storage cell

　　To solve the above problems, a new 6T-SRAM storage cell structure is proposed, as shown in Figure 2. NMOS tubes M5 and M6 are responsible for read operations, NMOS tubes M1, M4, PMOS tubes M2, M3 complete write operations, and only one bit line is involved in the read/write operation, so the power consumption of the entire unit is greatly reduced.

　　(1) Idle mode

　　In idle mode, that is, when neither the read operation nor the write operation is working, when O exists at Q point, M3 is turned on, Qbar is kept at VDD, and M2 and M4 are turned off. At this time, the data 0 at Q point may be affected by the leakage current IDS-M2 leakage accumulation, thereby generating a certain voltage at Q point, and even causing the Q point data to flip and generate erroneous logic. Therefore, the leakage current of M1 tube, mainly the subthreshold current of M1, needs to be utilized. For this purpose, the bit line needs to be turned on in idle mode.

Pull to ground, and keep the word line WL under subthreshold working condition, so that data 0 can be correctly stored without refreshing. When 1 exists at Q point, M4 and M2 are turned on, and there is positive feedback between Q and Qbar, so Q point is pulled to VDD by M2 tube, and Qbar is pulled to ground by M4 tube, but at this time M1 tube is under subthreshold condition, so there is a path from VDD to

, which will cause the Q point data to be unstable and may even flip. Since the current flowing through M2 is much larger than the current flowing through M1, the data is relatively stable. The other bit line BL is pulled to the ground. In idle mode, the leakage current at this end of the read path is very small and can be ignored.

　　(2) Write loop

　　The write 1 operation starts, WL high level turns on the M1 tube, and the read control tube RL is turned off.

Charging makes

=1, BL=0, Q point starts to charge to 1 (at this time, the NMOS tube transmits a weak 1), thereby turning on the M4 tube, making Qbar=0, and at the same time, positive feedback turns on the M2 tube, keeping the Q point at a strong 1; on the contrary, when writing 0, the bit line

Discharge to

=0, turn on the word line WL, Q=0, turn on the M3 tube at the same time, Qbar=1. After the write operation is completed, the cell enters the idle mode.

　　(3) Read loop

　　The read operation is mainly handled by M5 and M6 tubes. Qbar is connected to the gate of M5 tube, and BL is charged to a high level. When reading 1, Q=1, Qbar=0, M5 is closed, so the sensitive amplifier reads 1 from BL; when reading 0, the WL word line is closed, RL is turned on, Q=0, Qbar=1, tube M5 is turned on, M5 tube and M6 tube pull down BL together, and read data 0. After the read operation is completed, the unit enters idle mode.

2.1 Noise Tolerance

　　Noise tolerance is the maximum noise voltage value introduced into the storage node without causing the cell to flip. During the read operation, noise tolerance is more important for the stability of the cell, because in traditional SRAM, the read noise tolerance and the read current are in conflict. Increasing the read current speed will reduce the read noise tolerance at the expense of the read current. Therefore, in the traditional SRAM structure, the read current and the read noise tolerance cannot be adjusted separately and independently, and the two are mutually influenced and restricted. The new structure uses an independent read current path that does not include the storage node. Therefore, during the read operation, the voltage fluctuation and external noise on the bit line will hardly affect the storage node, thereby greatly increasing the read noise tolerance.

　　2.2 Leakage Current

　　From the above analysis, it can be seen that when the data is stored as 0, the new 6T-SRAM maintains the data through the subthreshold current of the M1 tube; when the data is stored as 1, due to the positive feedback of M2 and M4, and the fact that M1 is in a subthreshold conduction state in the idle state, there is a path from the power supply voltage to the ground, which will lead to an increase in leakage current. Figure 3 shows this path. In most data and instruction caches, the stored values ​​are mostly 0, accounting for 75% and 64% respectively. Based on these considerations, the average leakage current of ordinary 6T-SRAM and new 6T-SRAM was simulated under the standard 0.18μm CMOS process. The leakage current of the traditional 6T-SRAM is 164 nA, and the leakage current of the new 6T-SRAM is 179 nA. The new SRAM is 9% larger than the traditional one, which is within an acceptable range because the new SRAM adopts leakage current retention technology, so there is no need to refresh the data to maintain the data. In addition, leakage will not produce excessive floating voltage at the Q point, so the data is more stable.

　　2.3 Power consumption

　　Generally speaking, the bit line is the main part that generates dynamic power consumption, so the change of the bit line during the read/write operation conversion process often consumes the main power consumption. This paper simulates the power consumption of the traditional 6T-SRAM and the new 6T-SRAM cell structure, as shown in Table 1.

　　As can be seen from Table 1, in the traditional 6T-sRAM read/write process, the changes in the two bit line voltages of the symmetrical structure are consistent, so the power consumption is the same. The new 6T-SRAM cell power consumption is much lower than the traditional cell. This is because during the read/write operation, the number of tubes involved in the work is small, and only one bit line is involved in the work, and when writing 0, since the bit line is 0, the power consumption is very low.

　　2.4 Read/Write Simulation

　　In order to further verify the correctness of the new 6T-SRAM read/write function and compare it with the traditional 6T-SRAM unit, HSpice was used to perform read/write simulations on the two tubes, as shown in Figures 4 to 7.

　　The read/write simulation of the new 6T-SRAM memory cell shows that the read/write time of a single memory cell is within 0.2 ns, which meets the needs of the memory operating at a high speed.

　　3 Conclusion

　　The SRAM cell is simulated under 0.18μm process. The new SRAM adopts leakage current retention technology, so it does not need to be refreshed to maintain data. The simulation shows that the power consumption is much lower than that of traditional SRAM. The read/write speed is a little slower than that of traditional SRAM, but this is within an acceptable range.