Highly integrated NAND phase change memory solution that can apply three-dimensional storage structure PCM

A research team led by Professor Ken Takeuchi of the Department of Electrical, Electronic, Information and Communication Engineering, Faculty of Science and Technology, Chuo University, Japan, proposed a NAND-type phase change memory (PCM) solution and presented it at the International Memory Workshop (IMW) held in Milan, Italy from May 20 to 23, 2012. The selection element of this memory uses polysilicon MOS transistors, which allows the use of a simple NAND-type flash memory cell structure that does not require contacts. In theory, the area of ​​the memory cell can be reduced to 4F2, and the number of processes can also be reduced. Professor Takeuchi believes that this technology can be applied to "PCM using a three-dimensional memory cell structure, etc." represented by "BiCS (Bit-Cost Scalable)" (Takeuchi).

　　The RAM interface used in traditional PCM has a problem that the RESET time is at the 10ns level, while the SET time is at the 100ns level. The longer SET time will restrict the reading performance and increase the energy consumption.

　　Therefore, Professor Takeuchi and others at Chuo University did not use PCM as RAM, but used it for block erasure like NAND flash memory. The time-consuming SET operation is used as data erasure, and is used in "block erasure" to initialize all cells in the block at the same time. Then the high-speed RESET operation is used as the write operation. It is reported that by adopting this method, the write speed can be increased to 7.7 times and the energy consumption can be reduced by up to 70% compared with the traditional RAM interface whose performance is restricted by the long SET operation time. Takeuchi said that when PCM is applied to block erasure, "even when erasing two memory cells at the same time, its energy consumption will not reach 2 times." By adopting this operation method, PCM can be easily used for storage applications. But on the other hand, this method cannot perform random access.

　　The problem with NAND PCM is that write disturbance is prone to occur after using NAND strings. According to reports, in order to avoid disturbance during writing, the on-state current of the pass transistor must be increased to at least 4 times the minimum RESET current and the RESET voltage must be increased to more than 1.07 times.