DDS Devices Generate High-Quality Waveforms: Simple, Efficient, and Flexible

By Brendan Cronin

　　summary

　　Direct digital synthesis (DDS) technology is used to generate and condition high-quality waveforms and is widely used in many fields such as medicine, industry, instrumentation, communications, and defense. This article will briefly introduce the technology, explain its advantages and disadvantages, examine some application examples, and introduce some new products that will help promote the technology.

　　Introduction

　　A key requirement in many industries is to accurately generate, easily manipulate, and quickly change waveforms of different frequencies and types. Whether it is a wideband transceiver requiring an agile frequency source with low phase noise and excellent spurious-free dynamic performance, or an industrial measurement and control system requiring a stable frequency stimulus, the ability to quickly, easily, and economically generate adjustable waveforms while maintaining phase continuity is a critical design criterion, and this is where direct digital frequency synthesis technology excels.

　　Frequency Synthesis Tasks

　　Increasing spectrum congestion, coupled with the insatiable demand for lower power, higher quality measurement equipment, has driven the use of new frequency ranges and better utilization of existing frequency ranges. As a result, greater control over frequency generation has been sought, in many cases with the help of frequency synthesizers. These devices use a given frequency, fC, to generate a related target frequency (and phase), fOUT. The general relationship can be simply expressed as:

　　fOUT = εx × fC

　　The scaling factor εx is sometimes called the normalized frequency.

　　This equation is usually implemented using an algorithm of successive approximation of real numbers. When the scaling factor is rational, the ratio of two relatively prime numbers (the output frequency and the reference frequency) will be harmonically related. However, in most cases, εx may belong to a wider set of real numbers, and the approximation process will be truncated once it is within an acceptable range.

　　Direct Digital Frequency Synthesis

　　A practical implementation of a frequency synthesizer is direct digital frequency synthesis (DDFS), often referred to as direct digital synthesis (DDS). This technique uses digital data processing to produce a frequency and phase adjustable output that is related to a fixed frequency reference or clock source, f _C . In the DDS architecture, the reference or system clock frequency is divided by a scaling factor that is programmable using a binary tuning word to produce the desired frequency.

　　In short, a direct digital frequency synthesizer converts a series of clock pulses into an analog waveform, usually a sine wave, triangle wave or square wave. As shown in Figure 1, its main parts are: phase accumulator (generating data on the phase angle of the output waveform), phase-to-digital converter (converting the above phase data into instantaneous output amplitude data), and digital-to-analog converter (DAC) (converting the amplitude data into sampled analog data points)

Figure 1. Functional block diagram of a DDS system

　　For a sine wave output, the phase-to-digital converter is typically a sine lookup table (Figure 2). The phase accumulator counts in units of N and generates a frequency relative to fC according to the following equation:

　　in:

　　M is the tuning word resolution (24 to 48 bits)

　　N is the number of pulses of fC corresponding to the minimum incremental phase change of the phase accumulator output word.

Figure 2. Typical DDS architecture and signal path (with DAC).

　　Since changing N immediately changes the output phase and frequency, the system is inherently phase continuous, a critical attribute for many applications. No loop settling time is required, unlike analog systems such as phase-locked loops (PLLs).

　　The DAC is usually a high-performance circuit designed specifically for the DDS core (phase accumulator and phase-to-amplitude converter). In most cases, the resulting device (usually a single chip) is generally called a pure DDS or C-DDS.

　　Actual DDS devices generally integrate multiple registers to implement different frequency and phase modulation schemes. For example, the phase register stores the phase content that is added to the output phase of the phase accumulator. In this way, the phase of the output sine wave can be delayed corresponding to a phase tuning word. This is very useful for phase modulation applications in communication systems. The resolution of the adder circuit determines the number of bits of the phase tuning word, and therefore, also determines the resolution of the delay.

　　There are advantages and disadvantages to integrating a DDS engine and a DAC on a single device, but whether integrated or not, a DAC is needed to produce high-quality analog signals with ultra-high purity. The DAC converts the digital sinusoidal output to an analog sine wave, which can be single-ended or differential. Some key requirements are low phase noise, excellent wideband (WB) and narrowband (NB) spurious-free dynamic range (SFDR), and low power consumption. If it is an external device, the DAC must be fast enough to process the signal, so it is very common to have a built-in parallel port.

　　DDS and other solutions

　　Other methods of generating frequencies include analog phase-locked loops (PLLs), clock generators, and dynamically programming the output of a DAC using an FPGA. A simple comparison of these techniques can be made by examining spectral performance and power consumption. Table 1 shows the results of this comparison in a qualitative manner.

Table 1. DDS vs. Competing Technologies—High-Level Comparison

　　A phase-locked loop is a feedback loop that consists of a phase comparator, a divider, and a voltage-controlled oscillator (VCO). The phase comparator compares a reference frequency to an output frequency (usually divided by N). The error voltage generated by the phase comparator is used to adjust the VCO, thereby adjusting the output frequency. Once the loop is established, the output will maintain a precise relationship in frequency and/or phase to the reference frequency. PLLs have long been considered an ideal choice for applications that require low phase noise and high spurious-free dynamic range (SFDR) for high-fidelity and stable signals within a specific frequency band.

　　Because PLLs cannot accurately and quickly tune frequency outputs and waveforms, and their slow response limits their applicability to fast frequency hopping and some frequency-shift keying and phase-shift keying applications.

　　Other solutions, including field-programmable gate arrays (FPGAs) with integrated DDS engines -- coupled with off-the-shelf DACs to synthesize output sine waves -- can solve the frequency hopping problem of the PLL, but they have their own drawbacks. The main system drawbacks include higher operating and interface power requirements, higher cost, larger size, and additional software, hardware, and memory issues that system developers must consider. For example, using the DDS engine option in modern FPGAs to generate a 10 MHz output signal with a dynamic range of 60 dB requires up to 72 kB of memory space. In addition, designers need to accept and be familiar with the subtle trade-offs and architecture of the DDS core. From a practical perspective (see Table 2), the rapid development of CMOS processes and modern digital design techniques, as well as improvements in DAC topologies, have enabled DDS technology to achieve unprecedented levels of low power, spectral performance, and cost in a wide range of applications. Although pure DDS products will never achieve the performance and design flexibility of high-end DAC technology combined with FPGAs, the advantages of DDS in size, power, cost, and simplicity make it the first choice for many applications.

Table 2. Benchmark Analysis Summary - Frequency Generation Techniques (<50 MHz)

　　At the same time, it is important to point out that since DDS devices fundamentally generate output waveforms digitally, it can simplify the architecture of some solutions or create conditions for digital programming of waveforms. Although sine waves are often used to explain the function and working principle of DDS, modern DDS ICs can also easily generate triangular or square wave (clock) outputs, thereby eliminating the need for a lookup table in the former case and a DAC in the latter case, because integrating a simple and accurate comparator is sufficient.

　　DDS Performance and Limitations

　　Graphs and Envelopes: Sin(x)xx Roll-off

　　The actual output of the DAC is not a continuous sine wave, but a series of pulses with a sinusoidal time envelope. The corresponding spectrum is a series of images and aliased signals. The image is distributed along the sin(x)/x envelope (see the |Amplitude| plot in Figure 3). Filtering is necessary to suppress frequencies outside the band of interest, but it cannot suppress higher-order aliases that appear in the passband (for example, due to DAC nonlinearities)

　　The Nyquist criterion requires at least two samples per cycle to reconstruct the desired output waveform. Image responses occur at sampled output frequencies fCLOCK × fOUT . In this example, where fCLOCK = 25 MHz and fOUT = 5 MHz, the first and second images appear (see Figure 3) at fCLOCK × fOUT , i.e., 20 MHz and 30 MHz. The third and fourth images appear at 45 MHz and 55 MHz. Note that sin(x)/x zeros occur at multiples of the sampling frequency. When fOUT is greater than the Nyquist bandwidth (1/2fCLOCK), the first image will appear within the Nyquist bandwidth and will alias (e.g., a 15 MHz signal will alias down to 10 MHz). The aliased images cannot be filtered out of the output using a traditional Nyquist antialiasing filter.

Figure 3. Sin(x)/x roll-off in DDS.

　　In a typical DDS application, a low-pass filter is used to suppress the effects of image frequency responses in the output spectrum. In order to keep the cutoff frequency requirement of the low-pass filter at a reasonable level and keep the filter design simple, a practical approach is to use an economical low-pass output filter to limit the fOUT bandwidth to about 40% of the fCLOCK frequency.

　　The amplitude of any given image frequency relative to the fundamental can be calculated using the sin(x)/x formula. Since this function rolls off with frequency, the amplitude of the fundamental output will decrease inversely with the output frequency; in a DDS system, the decrease is –3.92 dB over the DC-Nyquist bandwidth.

　　The amplitude of the first image frequency is large - within 3 dB of the fundamental. To simplify the filtering requirements of a DDS application, a frequency plan must be developed and the spectral requirements of the image frequency and sin(x)/x amplitude response at the target frequencies of fOUT and fCLOCK must be analyzed. Online interactive design tools support the ADI DDS product family and can quickly and easily simulate the magnitude of the image frequency and allow the user to select frequencies where the image is outside the frequency band of interest. For more useful information, see the More Information and Useful Links section.

　　Other unwanted frequencies in the output spectrum, such as the DAC's integral and differential linearity errors, DAC-related spurious energy, and clock feedthrough noise, will not follow a sin(x)/x roll-off response. These unwanted frequencies will appear as harmonics and spurious energy in many places in the output spectrum - but their amplitudes will generally be much lower than the image response. The general noise floor of a DDS device is determined by a cumulative combination of substrate noise, thermal noise effects, ground coupling, and coupling from other signal sources. The noise floor, performance spurs, and jitter of a DDS device are profoundly affected by board layout, power supply quality, and - most importantly - the quality of the input reference clock.

　　Jitter

　　A perfect clock source would have edges that occur at precise intervals that would never vary. This is impossible, of course; even the best oscillators are made of imperfect components and have imperfections such as noise. A good, low-phase-noise crystal oscillator has jitter in the order of picoseconds, accumulated from millions of clock edges. Jitter is caused by thermal noise, oscillator circuit instability, and external interference from power, ground, and output connections, all of which can interfere with the oscillator's timing characteristics. In addition, oscillators are affected by external magnetic or electric fields and by radio frequency interference from nearby transmitters. A simple amplifier, inverter, or buffer in the oscillator circuit can also introduce additional jitter into the signal.

　　Therefore, it is critical to select a stable reference clock oscillator with low jitter and sharp edges. A higher frequency reference clock allows for greater oversampling, and jitter can be mitigated to some extent by dividing the frequency, because dividing the signal will produce the same amount of jitter over a longer period of time, thus reducing the percentage of jitter on the signal.

　　Noise - including phase noise

　　The noise of a sampling system depends on many factors, the first of which is the reference clock jitter, which appears as phase noise on the fundamental signal. In a DDS system, truncated phase register outputs can introduce code-dependent systematic errors. Binary words do not cause truncation errors. However, for non-binary words, phase noise truncation errors can produce spurs in the spectrum. The frequency/amplitude of the spurs depends on the code word. DAC quantization and linearity errors can also introduce harmonic noise into the system. Time domain errors such as undershoot/overshoot and code errors can add to the distortion of the output signal.

　　application

　　DDS applications can be divided into two categories:

　　Communications and radar systems requiring an agile frequency source for data encoding and modulation applications

　　Measurement, industrial, and optical applications requiring general purpose frequency synthesis functionality with programmable tuning, sweeping, and excitation capabilities

　　In both cases, there is a trend toward higher spectral purity (lower phase noise and higher spurious-free dynamic range), while there are also requirements for low power consumption and small size to accommodate the needs of remote or battery-powered equipment.

　　DDS in Modulation/Data Coding and Synchronization

　　DDS products first appeared in radar and military applications, and some of its characteristics (improved performance, cost, size, etc.) have made DDS technology increasingly popular in modulation and data encoding applications. This section will discuss two data encoding schemes and how to implement them in DDS systems.

　　Binary Frequency Shift Keying (BFSK, or FSK for short) is one of the simplest forms of data encoding. Data is transmitted by switching the frequency of a continuous carrier between two discrete frequencies (one is binary 1, i.e., pass, and the other is binary 0, i.e., space). Figure 4 shows the relationship between data and the transmitted signal.

Figure 4. Binary FSK modulation.

　　Binary 1 and 0 are represented by two different frequencies, f0 and f1. This encoding scheme can be easily implemented in DDS devices. The DDS frequency tuning word representing the output frequency is changed to generate f0 and f1 from the 1 and 0 to be transmitted. In ADI's pure DDS product family, at least two devices AD9834 and AD9838 (see Appendix), users can simply program the two current FSK frequency tuning words into the IC's embedded frequency registers. To change the output frequency, a dedicated pin FSELECT must be used to select the register containing the corresponding tuning word (see Figure 5)

Figure 5. FSK encoding using the tuning word selector of the AD9834 or AD9838 DDS.

　　Phase shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier wave remains constant, and information is conveyed by changing the phase of the transmitted signal. PSK can be implemented using a variety of schemes. The simplest method is usually called binary PSK (BPSK), which uses only two signal phases: 0° (logic 1) and 180° (logic 0). The state of each bit depends on the state of the previous bit. If the phase of the wave does not change, the signal state will remain the same (low or high). If the phase of the wave changes by 180°, that is, the phase is reversed, the signal state will change (low to high, or high to low). PSK encoding can be easily implemented in DDS products because most devices have a separate input register (phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, resulting in a PSK output. For applications that require high-speed modulation, the AD9834 and AD9838 have built-in phase register pairs that allow the signal on their PSELECT pins to shift between preloaded phase registers to modulate the carrier as needed.

　　More complex PSK uses four or eight wave phases. This allows the transmission rate of binary data to be higher than BPSK modulation each time a phase change occurs. In four-phase modulation (quadrature PSK), the possible phase angles are 0°, +90°, -90°, and +180°; each phase change can represent two signal factors. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers that allow complex phase modulation schemes to be implemented by continuously updating the registers with different phase offsets.

　　Implementing I/Q Functions Using Multiple DDS Elements in Synchronous Mode

　　Many applications require the generation of two or more sine or square wave signals with a known phase relationship. A common example is in-phase and quadrature modulation (I/Q), a technique in which signal information is derived from a carrier frequency at 0° and 90° phase angles. Two separate DDS components can be run from the same source clock to output signals whose phase relationship can be directly controlled and manipulated. In Figure 6, an AD9838 device is programmed with a single reference clock; the same RESET pin is used to update both devices. In this way, a simple I/Q modulation

　　RESET must be initialized after power-up and before any data is transmitted to the DDS. As a result, the DDS output is placed in a known phase, making it a common reference angle for synchronizing multiple DDS devices. When new data is sent to multiple DDS devices at the same time, the DDS can maintain a related phase relationship, or the relative phase offset between multiple DDSs can be predictively adjusted through the phase offset register. The AD983x series of DDS products have 12-bit phase resolution, with an effective resolution of 0.1°.

Figure 6. Synchronizing two DDS components.

　　For more information on synchronizing multiple DDS devices, see Application Note AN-605 Synchronizing Multiple AD9852 DDS-Based Frequency Synthesizers.

　　Network analysis

　　Many applications in the electronics world require collecting and decoding data from a network, such as analog measurements and optical communication systems. Normally, the system analysis requirement is to simulate a circuit or system at a frequency with known amplitude and phase, and analyze the characteristics of the response signal passing through the system.

　　The information gathered on the response signal is used to determine key system information. The scope of the test network (see Figure 7) can be very broad, including cable integrity testing, biomedical sensing, and flow measurement systems. Whenever the basic requirement is to generate a frequency-based signal and compare the phase and amplitude of the response signal to the original signal, or to stimulate a range of frequencies through the system, or test signals with different phase relationships (such as in systems with I/Q functions) are required, direct digital frequency synthesis ICs can be used to conveniently and elegantly control the excitation frequency and phase digitally through software.

Figure 7. Typical network analysis architecture using frequency excitation.

　　Cable integrity/loss measurements

　　Cable integrity measurement is a non-intrusive cable analysis method widely used in applications such as aircraft wiring, local area networks (LANs), and telephone lines. One way to determine performance is to see how much signal is lost while passing through the cable. By injecting a signal of known frequency and amplitude, the user can measure the amplitude and phase at the far end of the cable and calculate the cable attenuation. Parameters such as DC resistance and characteristic impedance will affect the attenuation of a specific cable. The result is usually expressed as a number of decibels below the signal source (0 dB) over the entire test frequency range. The target frequency depends on the cable type. DDS devices can be used as an excitation with the necessary frequency resolution because of their ability to generate a wide range of frequencies.

　　Flow Meter

　　A related application is flow analysis of water, other liquids, and gases in pipes. An example is ultrasonic flow measurement, which works on the principle of phase shift, as shown in Figure 8. Basically, a signal is transmitted from one end of a channel where the liquid is flowing, while a sensor is placed at the other end to measure the phase response (which depends on the flow rate). There are many variations of this technique. The test frequency depends on the substance being measured; in general, the output signal is transmitted over a range of frequencies. DDS has the flexibility to seamlessly set and change frequencies.

Figure 8. Ultrasonic flow meter.

　　More information and useful links

　　Interactive design tool

　　What is it? It is an online interactive design tool for DDS that assists in selecting the tuning word given a reference clock and desired output frequency and/or phase. The tool's programming calculations give the tuning word and other configuration bits for use in programming the device serial interface. After applying an external reconstruction filter, the ideal output harmonics for the selected reference clock and output frequency can be displayed. Links to ADI's design tools can be found on the interactive design tool home page. The AD9834 design tool is one example.

　　Evaluation Kit

　　The AD983x family of products comes with a fully functional evaluation kit complete with schematics and layout guidelines. The software provided in the evaluation kit allows the user to easily program, configure, and test the device (see Figure 9).

Figure 9. AD9838 evaluation software interface.

　　appendix

　　AD9838 Introduction: The functional block diagram of the AD9838 DDS is shown in Figure 10. This device is made using a fine-line CMOS process and is an ultra-low power (11 mW) pure DDS. The 28-bit frequency register supports 0.06 Hz frequency resolution and 16 MHz clock, as well as 0.02 Hz frequency resolution and 5 MHz clock. Phase and frequency modulation are configured through on-chip registers using software or pin selection. The device has a -68 dBc broadband and -97 dBc narrowband SFDR, and operates over the extended temperature range of –40°C to +125°C. The device is packaged in a small 4 mm × 4 mm, 20-lead LFCSP (lead frame chip scale) package.

Figure 10. Functional block diagram of the AD9838 DDS.

Brendan Cronin [brendan.cronin@analog.com] is a product marketing engineer in the Core Products and Technologies (CPT) group at Analog Devices. Brendan joined ADI in 1998 and spent six years as a mixed-signal design engineer in the Industrial and Automotive Products group. Brendan currently focuses on linear and related technologies.