Introduction to PIC 16C84 Microcontroller (I)

PIC16C84 is an 8-bit CMOS EEPROM microcontroller. It has high-performance RISC-like instructions, with a total of 35 single-byte instructions. All instructions require only one instruction cycle, except for program branch instructions, which require two instruction cycles. When the main oscillation frequency is 10MHZ, one instruction cycle is 400ns. The width of the program instruction is 14 bits, and there is a 1K×14 EEPROM program memory in the chip.

The data width is 8 bits. There are 36×8 static RAM general registers and 64×8 EEPROM data memory in the chip. 8-level deep hard stack. Direct, indirect and relative addressing modes. There are 4 interrupt sources: external RBO/INT pin; TMRO timer overflow, change of signal on PORTB<7: 4> pin; data writing to EEPROM completed.

The data memory can be erased/written up to 1,000,000 times, and the data retention is greater than 40 years. There are 13 I/O pins that can be directly controlled individually. Each I/O pin can withstand an input/output current of 25mA, so that the LED can be driven directly. There is an 8-bit timer/counter (TMRO) with an 8-bit programmable prescaler. There are power-on reset (POR); power rise (POWER-UP) timer (PWRT); oscillator start timer (OST); watchdog timer (WDT). In order to work reliably, it has its own RC oscillator. There is a code guarantee function. There is a SLEEP mode to save power consumption. There are 4 oscillators to choose from: RC (low-cost RC oscillator); XT (standard crystal/resonator); HS (high-speed crystal/resonator); LP (low-power, low-frequency crystal). The operating voltage range is wide from 2.0V to 6.0V.

The biggest feature of the PIC16C84 microcontroller is that it has a 1K×14-bit electrically erasable program memory and a 64×8-bit electrically erasable data memory, which will provide more convenience for system development and various applications.

Clock and instruction cycle

The clock input from OSCI is internally divided by 4. Non-superimposed clock cycles are generated, and each 4 clock cycles (θ1, θ2, θ3, θ4) constitute an instruction cycle. Each θ1 is added by 1 in the internal program counter, and then the instruction is fetched from the program memory. The fetched instruction is placed in the instruction register at θ4. The instruction is executed during the next θ1 and θ4. The instruction fetching and execution of instructions adopt pipeline technology. Instructions are fetched in one instruction cycle, and the fetched instruction is executed in the next instruction cycle, and the next instruction is fetched at the same time. Therefore, the CPU time for each instruction execution is one instruction cycle. When an instruction needs to change the content of the program counter (such as a branch instruction), it takes two instruction cycles to complete. The fetched instruction is placed in the instruction register at θ1 of the execution instruction cycle, and the instruction is decoded and executed at θ2, θ3, and θ4. The operand is read during θ2 and written during θ4.

Memory structure

There are two memory blocks in the PIC16C84 microcontroller. That is, the program memory and the data memory. Each block has its own bus, which means that each block can be accessed in the same clock cycle. The data memory is further divided into general purpose RAM and special function registers (SFRs). The special function registers are used to control the peripheral mode. The data memory also contains the data EEPROM memory. This memory is not directly mapped to the data memory, but indirectly mapped. That is, an indirect addressing pointer indicates the address of the data EEPROM to be read/written. The 64-byte data EEPROM has an address of 0 to 3FH.

3-1 Program Memory Structure

PIC16C84 microcontroller has a 13-bit program counter and an addressing capacity of 8K×14-bit program memory space. In fact, only 1K×14-bit program memory (address 0000～03FFH) is available for PIC16C84. If the address range exceeds the above unit, the address will wrap around. For example, the 20H unit and the address 420H, 820H, C20H, 1020H, 1420H, 1820H, 1C20H will all be accessed. When the system is reset, the PC value is 0000H and the interrupt vector is 0004H.

PC<12:0>

CALL, RETURN 13

RETFIE, RETLW Level 1 Stack

.

8-level stack

Reset address 0000H

External interrupt vector 0004H

User storage space 3FFH

1FFFH

3-2 Structure of Data Memory

The data memory is divided into two areas. The first is the dedicated function register (SFR) area, and the second is the general purpose register area (GPR). The SFR controls the operation of the device. The data memory is divided into block 0 and block 1. Block 0 (RP1=0, RP0=0) or block 1 (RP0=1) is selected by setting the RP1: RP0 bits in the status register STATUS during programming.

The parts with slashes are units that do not actually exist, and the units with * are not physically stored. The instructions MOVWF and MOVF can transfer the value of the W register (the W register is the working register inside the device) to any unit in the register file ("F"), and vice versa. The entire data memory can be addressed directly or indirectly through the file select register (FSR). Indirect addressing determines which block of the data memory to access based on the status of the RP1:RP0 bits in the status register. The two blocks of the data memory are divided into general registers and special registers. Each low-address unit is reserved for special registers, and the units with addresses above the special registers are general registers, which are static RAM.

1. General register file The register file can be addressed directly or indirectly through FSR. All devices have a certain number of general registers (GPR), and their data width is 8 bits. PIC16C84 has only 36 bytes of general registers, with addresses 0CH to 2FH. Access to 8CH to AFH corresponding to a block will actually access 0CH to 2FH (the high bits of the address are ignored).

File address

00 Indirect addressing address (*) Indirect addressing address (*) 80

01 TMRO OPTION 81

02 PCL PCL 8 2

03 STATUS STATUS 83

04 FSR FSR 8 4

05 PORTA TRISA 85

06 PORTB TRISB 86

07 87

08 EEDATA EECON1 88

09 EEADR EECON2(*) 89

0A PCLATH PCLATH 8A

0B INTCON INTCON 8B

36 general-purpose registers (SRAM) 0 block 2F AF 7F FF 0 block 1 block

2. Special Function Registers

The CPU and peripherals use special registers to control the operation of the device. Special registers are static RAM. The following are some important special registers.

① Status register

The status register contains the arithmetic status of the ALU (ALU), the reset status and the block selection for the data memory. Like any register, the status register can be used as the destination register for any instruction. If the status register is used as the destination register for an instruction, and that instruction affects the status of the Z, DC, and C bits, writing these three bits is prohibited. Figure 4-4 shows the status register and its status.

R/WR/WR/WRRR/WR/WR/W

IRP RP1 RP0 TO PD Z DC C bit7 bit0

Where C is the carry bit. For ADDWF and ADDLW instructions, when this bit is 1, it indicates that the most significant bit of the result of the instruction operation has produced a carry output. The subtraction instruction executes the new code of the second operand. For the loop instruction (RRF, RLF), this bit can come from the high bit or the low bit of the source register. If this bit is 0, it indicates that the most significant bit of the result has not produced a carry output. For subtraction, the polarity of this bit is inverted. DC is the digital carry or digital borrow bit. When this bit is 1, there is a carry from the D3 bit to the D4 bit of the result, otherwise there is no carry. For subtraction, the polarity of this bit is inverted. Z is the result 0 flag. When this bit is 1, it indicates that the result of arithmetic and logical operations is 0, otherwise this bit is 0, indicating that the result of the operation is not 0. PD: Low power bit. When this bit is 1, it indicates that the power is added to the normal power supply or after the C LRWDT instruction is executed. This bit is 0 to indicate that the SLEEP instruction is executed (that is, the device enters a low power state). TO timeout bit. When this bit is 1, it indicates that the power is on, the normal power supply is entered, and the CLRWDT and SLEEP instructions are executed. When this bit is 0, it indicates that the watchdog timer timeout occurs.

RP1:RP0, as the block select bits for directly addressed data memory.

RP1: RP=00 state, select block 0 (address 00H~7FH).

RP1: RP0=01 state, select 1 block (address 80H~FFH).

RP1: RP0=10 selects 2 blocks (address 100H~17FH).

RP1: RP0=11 selects 3 blocks (address 180H~1FFH).

Each block is 128 bytes. PIC16C84 only uses RP0 bit. RP1 is set to 0 when programming. It is not allowed to use RP1 as a general read/write bit, which may affect compatibility with future products. IRP register block selection bit (as indirect addressing). When this bit is set to 0, select block 0.1 (address 00H~FFH). When this bit is 1, select block 2.3 (address 100H~1FFH). PIC16C84 does not use IRP bit. IRP bit is 0 when programming. Z, DC, C bits in the status register are set or cleared according to the logic of the device. TO and PD bits are not writable. The result of the instruction with the status register as the destination register will have different contents. For example, CLRF STATUS (clear the status register). The content of the resulting status register is 000uuluu. Among them, u means no change. Only BCF, BSF, SWAPF and MOVW F instructions can be used to change the contents of the STATUS register because these instructions do not affect any status bits.

②OPTION register

The OPTION register is a readable and writable register that contains various control bits to configure the TMRO/WDT prescaler, external INT interrupt, TMRO and the weak pull-up on PORTB. Figure 4-5 shows the functions of each bit of the OPTION register. R/WR/WR/WR/WR/WR/WR/WR/ WR/W

RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0 bit7 bit0

PS2, PS1, and PS0 are the selections for the prescaler values. (Same as the PIC16C6X.) The PSA bit assigns the prescaler to the WDT (watchdog timer, or TMR0).

TOSE is the transition signal for TMRO

INTEDG is used to select the transition signal for the INT interrupt pin.

RBPU is used to turn on or off the internal pull-up resistor of PORTB.

The definition of all OPTION bits is the same as that of the PIC16C6X series.

③INTCON register

INTCON is a readable and writable register that contains the interrupt source to enable or disable interrupts. Figure 4-6 is the INTCON register of PIC16C84.

R/WR/WR/WR/WR/WR/WR/WR/WR/W

GIE EEIE TOIE INTE RBIF TOIF INTIF RB IF bit7 bit0

RBIF is the RB port change interrupt flag. When this bit is 1, it indicates that at least one bit in the RB<7:4> input has changed. It must be cleared to 0 by software. Otherwise, it is 0, that is, there is no change in the RB<7:4> input. INTIF is the external interrupt flag. When this bit is 1, it indicates that an external interrupt has occurred. It must be cleared to 0 by software. Otherwise, it is 0, indicating that no external interrupt has occurred.

TOIF is the TMRO overflow interrupt flag. This bit is 1, indicating that TMRO has overflowed, and must be cleared to 0 by software, otherwise it is 0, indicating that TMRO has not overflowed

RBIE is the enable or disable bit for the RB port change interrupt. Setting this bit to 1 enables the interrupt and to 0 disables it.

INTE is the enable or disable bit of the INT interrupt. Setting it to 1 enables the interrupt mode, and setting it to 0 disables it.

TOIE is the enable or disable bit for TMRO overflow interrupt. Set it to 1 to enable TMRO overflow interrupt, otherwise disable it.

EEIE is the enable and disable bit of the EE (Electrically Erasable) write completion interrupt. When set to 1, the EE write completion interrupt is allowed, otherwise it is disabled.

GIE is the enable and disable of all interrupts. When set to 1, all non-maskable interrupts are enabled, and 0 is disabled.

4. PCL and PCLATH

The program counter (PC) is a 13-bit register. The low byte PCL is a readable and writable register. The high byte of PC (PCH) is not directly readable and writable. PCLATH (PC latch high) is a holding register for PC<12:8>. The contents of these bits are transferred to the high bits of the program counter. When the program counter executes instructions such as CALL, GOTO or write PCL, a new value is loaded into the PC. The high bits of the PC are loaded by PCLATH.

There are 8 13-bit wide hardware stacks. The stack space is neither part of the program memory nor a part of the data memory, and the stack pointer is not readable/writable. When a CALL instruction is executed or an interrupt is responded to, the entire 13-bit PC is pushed into the stack. When executing RETURN, RETLW, RETFIE and other instructions, the stack is popped. PUSH (push) and POP (pop) do not affect PCLATH.

The stack is used as a circular buffer. When the stack is pushed 38 times, the 9th push will take the place of the first push, the 10th push will take the place of the second push, and so on. Similarly, when the stack is popped for the 9th time, it is the same as the first pop. Note that there is no status bit to indicate the stack overflow or underflow condition. There are no PUSH and POP instruction mnemonics, but the execution of CALL, R ETURN, RETLW, RETFIE and other instructions or the occurrence of an interrupt will actually push and pop the stack.

4-2 Program Memory Pages

PIC16C84 has 1K of program memory, and the CALL and GOTO instructions have only an 11-bit address range. This 11-bit address range allows branches within the 2K program memory page size range.

For future expansion of the PIC16C8X program memory, two additional bits are required to describe the program memory page. These page bits come from PCLATH<4:3>. When executing CALL, GOTO instructions, the user must ensure that the programming of these page bits points to the required program memory page.

If a CALL instruction is executed, the entire 13 bits are pushed onto the stack. Therefore, the management of the PCLATH<4:3> bits is not required for the return instruction. Because the value of the PC will be obtained by popping the stack. Note: The PIC16C84 ignores the PCLATH<4:3> bits, which are used for program storage pages 1, 2, and 3 (0800H-1FFFH). The PCLATH<4:3> bits of the PIC16C84 cannot be used as general read/write bits, which will affect the upward compatibility of future products.

4-3 Indirect addressing, the role of INDF and FSR

The INDF register is not a physical register, but is used in conjunction with the FSR register to perform indirect addressing.

Using the INDF register, indirect addressing can be achieved.

For any instruction using the INDF register, the actual data to be addressed is determined by the File Select Register (FSR). Reading INDF itself (FSR = 0) will produce 00H. Writing to INDF results in no operation (obviously providing status bits). The 8-bit FSR register is combined with the status register STATUS<7> (IRP) to obtain a 9-bit address.

However, PIC16C84 does not use IRP. Use the following program to clear the 2OH~2FH units through indirect addressing.

MOVLW 20H ; Initialize RAM pointer

MOVF FSR ; to FSR

NEXT CLRF INDF; Cleared to 0 through indirect addressing, the register pointed to by the content of FSR.

INCF FSR ;(FSR)+1→FSR

BIFSS FSR, 4; when the 4th bit of FSR is 1, skip the next instruction

GOTO NEXT; otherwise enter.