Analysis and comparison of various ADCs

A/D conversion technology

Today's software radio and digital image acquisition require high-speed A/D sampling to ensure effectiveness and accuracy. General measurement and control systems also hope to make breakthroughs in accuracy. The wave of human digitization has promoted the continuous transformation of A/D converters, and A/D converters are the pioneers of human digitalization.

Successive approximation type, integral type, voltage-frequency conversion type, etc. are mainly used in medium-speed or relatively low-speed, medium-precision data acquisition and intelligent instruments. Hierarchical and pipeline ADCs are mainly used in transient signal processing, fast waveform storage and recording, high-speed data acquisition, video signal quantization, and high-speed digital communication technology under high-speed conditions. In addition, high-speed ADCs using structures such as pulsation and folding types can be used in baseband demodulation in broadcast satellites. ∑-Δ ADCs are mainly used in high-precision data acquisition, especially in electronic measurement fields such as digital audio systems, multimedia, seismic exploration instruments, and sonar. The following is a brief introduction to various types of ADCs.

1. Successive approximation ADC

The successive approximation ADC is a widely used analog/digital conversion method, which includes a comparator, a digital-to-analog converter, a successive approximation register (SAR), and a logic control unit. It continuously compares the sampled input signal with the known voltage, completes a 1-bit conversion in 1 clock cycle, and N-bit conversion requires N clock cycles. After the conversion is completed, a binary number is output. The resolution and sampling rate of this type of ADC are contradictory. When the resolution is low, the sampling rate is high. To improve the resolution, the sampling rate will be limited.

Advantages: Lower price for resolutions below 12 bits, sampling rates up to 1MSPS; power consumption is quite low compared to other ADCs.

Disadvantages: Higher price at resolutions above 14 bits; the signal generated by the sensor needs to be conditioned before analog-to-digital conversion, including gain stages and filtering, which significantly increases costs.

2. Integrating ADC

The integrating ADC is also called dual slope or multi-slope ADC, and it is widely used. It consists of an analog integrator with an input switching switch, a comparator and a counting unit. It converts the input analog voltage into a time interval proportional to its average value through two integrations. At the same time, the counter is used to count the clock pulses in this time interval to achieve A/D conversion.

The integration time of the integrating ADC is determined by the same clock generator and counter, so the obtained D expression is independent of the clock frequency, and its conversion accuracy depends only on the reference voltage VR. In addition, since the input end uses an integrator, it has a strong ability to suppress the interference of AC noise. It can suppress high-frequency noise and fixed low-frequency interference (such as 50Hz or 60Hz), and is suitable for use in noisy industrial environments. This type of ADC is mainly used in low-speed, precision measurement and other fields, such as digital voltmeters.

Advantages: high resolution, up to 22 bits; low power consumption and low cost.

Disadvantages: Low conversion rate, the conversion rate is 100~300SPS when it is 12 bits.

3. Parallel comparison A/D converter

The main feature of the parallel comparison ADC is its high speed. It is the fastest of all A/D converters. Most modern high-speed ADCs use this structure, and the sampling rate can reach more than 1GSPS. However, due to power and volume limitations, it is difficult to achieve a high resolution for the parallel comparison ADC.

The conversion of all bits of the ADC of this structure is completed at the same time, and its conversion time mainly depends on the switching speed of the comparator, the transmission time delay of the encoder, etc. Increasing the output code has little effect on the conversion time, but as the resolution increases, high-density analog design is required to realize the large number of precision voltage divider resistors and comparator circuits required for conversion. When the output number increases by one bit, the number of precision resistors will double, and the number of comparators will also approximately double.

The resolution of the parallel comparison ADC is limited by the die size, input capacitance, power, etc. As a result, repeated parallel comparators will cause static errors if their accuracy is not matched, such as increasing the input offset voltage. At the same time, this type of ADC will also produce discrete and inaccurate outputs, the so-called "spark code", due to the metastable voltage and coding bubbles of the comparator.

Advantages: Highest analog/digital conversion speed.

Disadvantages: low resolution, high power consumption and high cost.

4. Voltage-to-frequency conversion ADC

The voltage-frequency conversion ADC is an indirect ADC. It first converts the voltage of the input analog signal into a pulse signal whose frequency is proportional to it, and then counts the pulse signal at a fixed time interval. The counting result is a digital quantity proportional to the input analog voltage signal. Theoretically, the resolution of this ADC can be increased infinitely, as long as the width of the accumulated pulse number is long enough to meet the output frequency resolution requirement.

Advantages: high accuracy, low price, low power consumption.

Disadvantages: Similar to integrating ADCs, its conversion rate is limited to 100 to 300 SPS for 12 bits.

5.∑-Δ ADC

The ∑-Δ converter is also called an oversampling converter. It uses incremental coding, that is, quantization coding is performed based on the difference between the previous value and the next value. The ∑-Δ ADC includes an analog ∑-Δ modulator and a digital decimation filter. The ∑-Δ modulator mainly completes signal sampling and incremental coding. It provides incremental coding, namely ∑-Δ code, to the digital decimation filter; the digital decimation filter completes the decimation filtering of the ∑-Δ code, and converts the incremental coding into a high-resolution linear pulse code modulated digital signal. Therefore, the decimation filter is actually equivalent to a code converter.

Advantages: high resolution, up to 24 bits; high conversion rate, higher than integral and voltage-frequency conversion ADCs; low price; internal use of high-frequency oversampling technology to achieve digital filtering, reducing the requirements for filtering sensor signals.

Disadvantages: The price of high-speed ∑-△ ADC is relatively high; under the condition of the same conversion rate, the power consumption is higher than that of integral and successive approximation ADCs.

6. Pipeline ADC

The pipeline structure ADC, also known as the sub-area ADC, is an efficient and powerful analog-to-digital converter. It can provide high-speed, high-resolution analog-to-digital conversion, and has a satisfactory low power consumption and a small chip size; after reasonable design, it can also provide excellent dynamic characteristics.

The pipeline ADC consists of several cascaded circuits, each of which includes a sample/hold amplifier, a low-resolution ADC and DAC, and a summing circuit, where the summing circuit also includes an interstage amplifier that can provide gain. The fast and accurate n-bit converter is divided into more than two sub-areas (pipeline) to complete. After the sample/hold of the first stage circuit samples the input signal, it is first quantized by an m-bit resolution coarse A/D converter, and then a product-type digital-to-analog converter (MDAC) with at least n-bit accuracy is used to generate an analog/analog level corresponding to the quantization result and sent to the summing circuit, which deducts this analog level from the input signal. The difference is accurately amplified by a fixed gain and then handed over to the next stage circuit for processing. After such processing at each stage, the residual signal is finally converted by a higher-precision K-bit fine A/D converter. The outputs of the above-mentioned coarse and fine A/Ds are combined to form a high-precision n-bit output.

Advantages: good linearity and low offset; can process multiple samples simultaneously, with high signal processing speed, typically Tconv <100ns; low power; high precision; high resolution; can simplify the circuit.

Disadvantages: The reference circuit and bias structure are too complicated; the input signal needs to be specially processed in order to pass through several stages of circuits to cause pipeline delays; the requirements for latch timing are strict; the circuit process requirements are very high, and unreasonable design on the circuit board will affect the linearity of the gain, offset and other parameters.

At present, this new ADC structure is mainly used in communication systems with high requirements for THD, SFDR and other frequency domain characteristics, CCD imaging systems with high requirements for time domain characteristics such as noise, bandwidth and transient response speed, and data acquisition systems with high requirements for both time domain and frequency domain parameters.

After determining the design plan for the A/D conversion device, you first need to clarify the required index requirements for A/D conversion, including data accuracy, sampling rate, signal range, etc.

1. Determine the number of bits of the A/D converter. Before selecting an A/D device, it is necessary to clearly define the accuracy that the design is going to achieve. Accuracy is a physical quantity that reflects the degree of accuracy of the actual output of the converter close to the ideal output. During the conversion process, due to the existence of quantization error and system error, the accuracy will be lost. Among them, the impact of quantization error on accuracy is calculable, and it is mainly determined by the number of bits of the A/D converter. The number of bits of the A/D converter can be expressed by resolution. Generally, A/D converters with less than 8 bits are called low-resolution ADCs, 9 to 12 bits are called medium-resolution ADCs, and 13 bits and above are high-resolution. The higher the number of bits of the A/D device, the higher the resolution, the smaller the quantization error, and the higher the accuracy that can be achieved. In theory, the accuracy of the system can be infinitely improved by increasing the number of bits of the A/D device. But this is not the case. Since the circuit of the A/D front end will also have errors, it also restricts the accuracy of the system.

For example, when using A/D to collect the signal provided by the sensor, the accuracy of the sensor will restrict the accuracy of A/D sampling. The accuracy of the signal after A/D acquisition cannot exceed the accuracy of the sensor output signal. When designing, the accuracy required by the system and the accuracy of the front-end signal should be comprehensively considered.

2. Select the conversion rate of the A/D converter. In different applications, the requirements for conversion rate are different. In the same application, the accuracy requirements are different, and the sampling rate will also be different. The sampling rate is mainly determined by the sampling theorem. After the application is determined, the sampling rate can be calculated using the sampling theorem according to the characteristics of the collected signal object. If digital filtering technology is used, oversampling must also be performed to increase the sampling rate.

3. Determine whether a sample/hold device is needed. The sample/hold device is mainly used to stabilize the signal quantity and realize flat-top sampling. For the acquisition of high-frequency signals, the sample/hold device is very necessary. If you are acquiring DC or low-frequency signals, you may not need a sample/hold device.

4. Choose the right range. The dynamic range of analog signals is large, and sometimes negative voltage may appear. When choosing, the dynamic range of the signal to be measured should be within the range of the A/D device to reduce additional hardware efforts.

5. Choose the right linearity. In the A/D acquisition process, the higher the linearity, the better. However, the higher the linearity, the higher the price of the device. Of course, the impact of nonlinearity can also be reduced through software compensation. Therefore, when designing, factors such as accuracy, price, and difficulty of software implementation should be considered comprehensively.