AD1674 Application Circuit

AD1674 Application Circuit

1 Hardware Design
1.1 AD1674 Interface Circuit
Reference [1] introduces the performance of the AD1674 chip and the timing of the control signal in detail. In a fully controlled mode, it is best to use the logic control signal CE to start data reading or A/D conversion; when CE is valid, the chip select signal CS should be valid, and the control signals R/C and A0 are determined. Only when this timing is met can the AD1674 work normally.

1.2 A/D conversion and data reading timing
For the A/D interface circuit, only when the timing of the PC matches the required timing of AD1674 can the normal operation of the circuit be guaranteed. The A/D conversion and data reading timing of the circuit are shown in Figure 1.

During A/D conversion, the timing pulse of 8253 or the port write pulse QD, after delay and adjustment of the timing width, enables the A/D enable control CE to start the A/D conversion. At the same time, the low-level pulse with a width of 1μs (in the port write start mode, the low pulse of 1μs is obtained by adjusting the timing width of the port write pulse) enables the conversion of R/C. A0 and chip select CS can be set to be valid before A/D conversion. When reading the data after A/D conversion, the port read signal or DMA read signal D directly enables the enable control CE of A/CD to start data reading. At this time, R/C=1, the reading of R/C is valid, and the reading of 12-bit data begins. When A0=0, read the upper eight bits of data; when A0=1, read the lower four bits of data. After reading, A0=0, prepare for the next A/D conversion. It can be seen that this timing can not only interface with the PC, but also make the AD1674 work normally.

1.3 Implementation circuit of A/D conversion and data reading
The AD1674 in this circuit works in a fully controlled mode. The A/D conversion is 12 bits, and the converted data is read twice, that is, the upper eight bits of the data are read first, and then the lower four bits of the data are read.

1.3.1 How to start A/D conversion

There are two ways to start A/D conversion: 8253 timer hardware start and write port software start.

The 8253 timer start mode is used in situations where the time interval of data acquisition is required to be accurate. This mode uses the timing pulse of 8253 to start A/D conversion, outputs the initial count value of the identification channel through the 8253 data bus buffer (port address is &0X23F), and sets the control word of 8253 and the A/D chip select control bit by writing the control word to the 6-bit latch 74LS174 (port address is &0X23B). The 6-bit latch
data bit definition is as follows:
A1A0=00: &0X23D The data output by the port is the count value of counter 0.
A1A0=01: &0X23F
The data output by the port is the count value of counter 1. A1A0=10: &0X23F The data output by the port is the count value of counter 2.
A1A0=11: &0X23F The data output by the port is the mode word of counter 8253.
G0&G1=1: start counter 0 and counter 1; G0&G=0: disable counter 0 and counter 1.
CS=1: select A/D chip CS=0: do not select A/D chip.

The specific implementation circuit is shown in Figure 2. First, connect the 8253 timing channel 0 and channel 1 in series for timing. The frequency of the clock input CLK0 of channel 0 is 2MHz. When working in mode 3 (square wave ratio generator), the output OUT0 of channel 0 is a square wave with a frequency of 1MHz, which serves as the input clock CLK1 of channel 1. Channel 1 is set to mode 2, that is, the output OUT1 of channel 1 maintains a high level from the beginning of output. After the count returns to zero, the output is low and the original count value is automatically reloaded. After the low level is maintained for one clock cycle, the output returns to a high level and counts down again. The output OUT1 is divided into two signals, one of which is output through the AND gate U18A as the R/C control signal of AD1674; the other is output through the OR gate U15C as the CE control signal of AD1674 after the monostable trigger U24 delays and adjusts the timing width. When OUT1 outputs a low-level pulse with a width of 1μs, on the one hand, the conversion of the control signal R/C is effective, and at the same time, after delaying and adjusting the timing width, the A/D enable control CE starts the A/D conversion. Therefore, after loading the initial count value, as long as the control word of the 6-bit latch U8 is set, the 8253 timer can be used to start the A/D.

The write-start A/D mode is applied to software timing, that is, triggering A/D conversion by writing to the port (address is &0X23D). As shown in Figure 2
, the port write signal is used as the R/C control signal of AD1674 after adjusting the timing width (width is 1μs) through the monostable trigger U6A. At the same time, after delaying and adjusting the timing width through another monostable trigger U24, it is output as the CE control signal of AD1674 through the OR gate U15C.

It can be seen that the two processes of starting A/D conversion are similar. In comparison, the sampling interval of the former is determined by the period of the 8253 timing pulse
, which belongs to the programmable timer timing method, and the common feature is accurate sampling interval; the latter is
determined by the time difference between two adjacent write ports (address is &0X23D), which is a software timing method, and the feature is flexibility and convenience.

1.3.2 Reading methods of A/D conversion data
In the data acquisition system, there are generally three ways for the computer to read A/D conversion data, namely query, interrupt and DMA. The query method is to determine whether the A/D conversion is completed by querying the flag bit. If the A/D conversion is completed, the converted data is read in. In this method, the CPU actively queries and reads the A/D conversion data through the CPU, so the hardware circuit implemented is simple, but the data reading speed is slow. At the same time, in the multi-task execution mode of WINDOWS, there is a problem that the A/D conversion data cannot be read in time. The interrupt method uses the flag bit of the A/D conversion completion to trigger a hard interrupt, and then the interrupt manager submits an interrupt request to the CPU. When the interrupt is allowed, the interrupt service program is executed to read the converted data. The hardware circuit implemented in this way is also relatively simple, but the intervention of the interrupt service program causes
the unpredictability of the breakpoint of the data acquisition program, which will cause the data acquisition program to lose control. The DMA method uses the A/D conversion completion
flag to submit a DMA request to the DMA controller. When the DMA controller obtains bus control from the CPU, the interface directly exchanges data with the memory (without passing through the CPU). In this method, the data transmission speed is improved because the data is not read through the CPU. At the same time, since the A/D converter actively requests data transmission, and the DMA request has a higher priority than the peripheral interrupt request, the A/D conversion data can be read in time, and the system performance is also improved, but the hardware circuit implemented is more complex than the previous two methods.

This circuit is designed with three data transmission modes: query, interrupt and DMA. Different transmission modes are selected by a dial switch. As shown in Figure 3, when the A/D conversion is completed, the flag bit STS changes from high level to low level, thereby triggering the D flip-flop U20A, and the output Q of U20A changes from low level to high level. When the dial switch S1 is selected as the query mode, the output Q of U20A is connected to the data line D6 through a three-state gate (port address is &0X23F) to provide computer query; in the interrupt mode, the output Q of U20A is directly connected to the hard interrupt pin IRQ2, and when Q changes from low level to high level, it causes a computer interrupt. In the first two modes, through software programming, write 0 or 1 to the lowest bit of a latch U22, select to read the high eight bits or low four bits of the A/D conversion data, and read the A/D conversion data by a dedicated port (address is &0X23D). The hardware circuit implemented is simple. In DMA mode,
the A/D conversion data is not read by a dedicated port, and
the function of selecting the high eight bits or low four bits of the A/D conversion data must be implemented by hardware circuits. In comparison, the circuit is more complicated.

The following introduces the specific implementation circuit under DMA mode. The DMA request circuit consists of two D flip-flops. When the A/D conversion is completed, the output Q of U20A changes from low level to high level, DRQ1=1, and DMA channel 1 issues a request. After DRQ1 is recognized, two DMA transfers are performed. During the first DMA transfer, the output Q of flip-flop U20B is low level, and the upper eight bits of the A/D conversion data are transferred to the specified memory unit. At the end of the first DMA transfer, DACK1 changes from low level to high level, the output of flip-flop U20B is high level, but the output Q of flip-flop U20A is still high level, which requests the second DMA transfer. During the second DMA transfer, the output of flip-flop U20B is high level, and the lower four bits of the A/D conversion data are transferred to the specified memory unit. When the second DMA transfer ends, DACK1 changes from low level to high level, causing trigger U20B to output low level. At the same time, the output Q of trigger U20A becomes low level, DRQ1=0 becomes low level, DRQ1=0, and the request of DMA channel 1 is revoked, ending an A/D conversion 12-bit data transmission process.

2 Software Design
This interface circuit supports various high-level languages ​​with port instruction operations and 8086/8088 assembly language. The following takes Turbo C as an example to
program the corresponding parts for reference.

2.1 A/D programming
This programming is suitable for programming in interrupt or query mode, port address = 0x238 ~ 0x23f.
outportb(0x23c,0x00); /*initialize and clear*/
outportb(0x23a,0x00); /*select to transmit high 8-bit data and prepare for A/D conversion*/
{
}; /*start A/D and check whether A/D conversion is completed*/
dh=inportb(0x23d); /*input high 8-bit data*/
outporth(0x23a,0x01); /*select to transmit low 4-bit data*/
dl=inportb(0x23d); /*input low 4-bit data*/
outportb(0x23a,0x00); /*select to transmit high 8-bit data and prepare for A/D conversion*/
dl=dl>>4;
dh1=dh;
dl=(dh1<<4)+dl;
dh=dh>>4; /*convert high 8-bit and low 4-bit data into high 4-bit and low 8-bit data*/
d=dh*256+dl; /*merge 12-bit data*/
u=(d-2047)*10.0/4096; /*convert voltage value*/
2.2 Write start and query mode programming
outportb(0x23d,0x00); /*Write start A/D conversion*/
if(inporth(0x23e)&0x80);/*D7=1 then A/D conversion is completed*/
2.3 8253 timer programming
outportb(0x23b,0x03); /*set 8253 timer into writing mode word state*/
outportb(0x23f,0x36); /*set 0 channel working with mode 3*/
outportb(0x23f,0x74); /*set 1 channel working with mode 2*/
outportb(0x23b,0x00); /*set to write data to 0 Channel mode */
outportb(0x23f,0x02); /*write low data to 0 channel*/
outportb(0x23f,0x00); /*write high data to 0 channel*/
outportb(0x23b,0x01); /*set to write data to 1 channel*/
outportb(0x23f,LC1); /*write low data to 1 channel*/
outportb(0x23f,HC1); /*write high data to 1 channel*/
outportb(0x23b,0x0c); /*Start CH0, CH1 working*/
The sampling frequency is determined by the count value written into counter 1.
2.4 Programming 8237A DMA controller in PC host under DMA mode
The 8237A DMA controller has 4 DMA channels, and this interface circuit uses channel 1.
outportb(0x0x,0x05); /*mask DMA channel 1*/
outportb(0x0c,0x00); /*clear byet pointer flip*/
outportb(0x0b,0x55); /*write mode word.demand mode,address tincrease，autoinitialization,write trasfer
and select 1*/
outportb(0x83,SEG); /*write page number*/
outportb(0x02,LA); /*write low 8 bit address*/
outportb(0x02,HA); /*write high 8 bit address*/
outportb(0x03,LC); /*write low 8 bit count data*/
outportb(0x03,HC); /*write high 8 bit count data*
outportb(0x03,0x01); /*clear mask bit of DMA channel*/
The value written to port 11 should be determined according to the specific working mode. Write 131 The page address SEG of the port takes the highest 4 bits of the 20-bit absolute address, and writes the lower 16-bit address value into the address register. The total number of bytes written into the base value byte count register should be the number of bytes to be transferred minus 1.
2.5 Writing the interrupt service program Loading with interrupt vector
void interrupt int9() /*Interrupt service program*/
{ disable();
ah5=inportb(0x23d); /*Input high 8-bit data*/
outportb(0x23a,0x01); /*Select to transfer low 4-bit data*/
dl5=inportb(0x23d); /*Input low 4-bit data*/
outportb(0x23a,0x00); /*Select to transfer high 8-bit data and prepare for A/D conversion*/
outportb(0x23c,0x00); /*Clear the flag bit of A/D conversion completion*/
outportb(0x20,0x20);
enable();
}
void stall 1(void interrupt(*faddr)())
{
disable();
setvect(INT1,faddr); /*Load interrupt service program*/
enable();
}
This paper introduces an interface circuit based on AD1674. The circuit has three data transmission functions: query, interrupt and DMA. At the same time, it adopts two A/D start modes: 8253 timing pulse or port write. Among them, DMA mode realizes fast data transmission, and the two A/D start modes will make the setting of sampling rate more flexible. The data acquisition board that can be inserted into a general PC and designed by applying the principles of this paper has been used in our high-frequency Doppler and arrival angle detection analysis system, and achieved satisfactory results. These design methods and principles will also have important reference value in the design process of other actual data acquisition systems.

Application Circuit

Figure 6 is a circuit diagram of the data acquisition and processing part of a new domestic airborne weapon system .
The sixteen analog signals from the sensors are switched by multiple switches
and sent to the high-precision op amp for buffer amplification, while
maintaining the sampling accuracy of the signal. AD1674T is connected
to the ±10V bipolar analog voltage input mode, using
the internal reference source and clock. From the switch selection of the analog signal
to the A/D conversion and data output, the ADSP2100
microprocessor performs logic control. Each such conversion
cycle is 64μs, so it takes about 1ms to complete the analog conversion of 16 channels, which can meet the response technical requirements of the system
.