Analysis and comparison of several analog-to-digital conversion technologies

    Abstract: Compares several of the most commonly used analog-to-digital conversion technologies and their characteristics, focusing on introducing the latest analog-to-digital conversion technology - pipeline technology; elaborating on its working principle, performance characteristics and advantages to help readers make better choices Analog-to-digital converter suitable for your own design.

introduction

Analog-to-digital conversion is a technology that converts analog input signals into N-bit binary digital output signals. The use of digital signal processing can easily implement various advanced adaptive algorithms and complete functions that cannot be achieved by analog circuits. Therefore, more and more analog signal processing is being replaced by digital technology. Correspondingly, the application of analog-to-digital conversion as a bridge between analog systems and digital systems is becoming increasingly widespread. In order to meet the needs of the market, various chip manufacturing companies continue to launch new products and new technologies with more advanced performance, which is dizzying. This article analyzes and compares several of the most commonly used analog-to-digital conversion technologies.

1 Analog-to-digital conversion technology

Analog-to-digital conversion includes four processes: sampling, holding, quantization and programming. Sampling is to convert a continuously changing signal x(t) into a time-discrete sampling signal x(n). According to the Nyquist sampling theorem, for the sampled signal x(t), if the sampling frequency fs is greater than or equal to 2fmax (fmax is the highest frequency component of x(t)), the original signal x(t) can be reconstructed without distortion. In fact, due to the influence of factors such as nonlinear distortion of analog-to-digital converter devices, quantization noise, and receiver noise, the sampling rate is generally fs=2.5fmax. Usually the width of the sampling pulse tw is very short, so the sampling output is an intermittent narrow pulse. To digitize a sampled output signal, the instantaneous analog signal obtained from the sampled output needs to be maintained for a period of time. This is the holding process. Quantization is to convert continuous amplitude sampling signals into discrete time and discrete amplitude digital signals. The main problem of quantization is the quantization error. Assuming that the noise signal is uniformly distributed among the quantization levels, the quantization noise mean square value is related to the quantization interval and the input impedance value of the analog-to-digital converter. Encoding is to encode the quantized signal into a binary code and output it. Some of these processes are combined. For example, sampling and holding are completed continuously using a circuit. Quantization and encoding are also implemented at the same time during the conversion process, and the time used is part of the hold time. There are many technologies to implement these processes, ranging from the integral type that appeared as early as the 1970s to the latest pipeline analog-to-digital conversion technology. Due to different principles, their performance characteristics are different.

1.1 Integral analog-to-digital converter

Integrating analog-to-digital converters, called dual-slope or multi-slope data converters, are the most widely used converter type. A typical example is a dual-slope converter, and we will take this as an example to illustrate the working principle of the integral analog-to-digital converter. A dual-slope converter consists of two main parts: a circuit that samples and quantizes the input voltage to produce a time-domain interval or pulse sequence, which is then converted to a digital output by a counter, as shown in Figure 1.

    The dual slope converter consists of an analog integrator with an input switch, a comparator and a counting unit. The integrator integrates the input voltage over a fixed time interval, which usually corresponds to the maximum number of grounds of the internal counting unit. After the time has elapsed the counter is reset and the integrator input is connected to the inverse (negative) reference voltage. Under the action of this reverse polarity signal, the integrator is "reverse integrated" until the output returns to zero, causing the counter to terminate and the integrator to reset.

The sampling speed and bandwidth of integrating analog-to-digital converters are very low, but their accuracy can be very high, and their ability to suppress high-frequency noise and fixed low-frequency interference (such as 50Hz or 60Hz) makes them ideal for noisy industries. environments and applications that do not require high slew rates (such as quantification of thermocouple output).

1.2 Successive approximation analog-to-digital converter

The successive approximation converter includes a comparator, a digital-to-analog converter, a successive approximation register (SAR) and a logic control unit, as shown in Figure 2. The successive approximation in the conversion is completed by the control logic circuit according to the bisection principle. The general process is as follows: After starting the conversion, the control logic circuit first sets the highest position of the successive approximation register to 1 and other positions to 0. After digital-to-analog conversion, the content of the successive approximation register obtains a voltage value that is approximately half of the full-scale output. This voltage value is compared with the input signal in the comparator. The output of the comparator is fed back to the digital-to-analog converter and corrected before the next comparison. Driven by the clock of the logic control circuit, the successive approximation register continuously performs comparison and shift operations until the conversion of the least significant bit (LSB) is completed. At this time, the values ​​of each bit in the successive approximation register have been determined, and the successive approximation conversion is completed.

Since the successive approximation analog-to-digital converter can only complete 1-bit conversion in 1 clock cycle. N-bit conversion requires N clock cycles, so the sampling rate of this analog-to-digital converter is not high and the input bandwidth is low. Its advantage is that the principle is simple, easy to implement, there is no delay problem, and it is suitable for occasions with medium speed and high resolution requirements.

1.3 Flashing analog-to-digital converter

Compared with ordinary analog-to-digital converters, flash-type analog-to-digital converters are the fastest. Since there is no need for successive comparisons, it does not convert N-bit data N times, but only once, so the speed is greatly improved. Figure 3 shows the principle of an N-bit flashing analog-to-digital converter. There is a certain reference voltage in the converter, and the analog input signal is simultaneously added to 2N-1 latched comparators. The reference voltage of each comparator is derived from a voltage divider formed by a resistor network, and its reference voltage is one least significant bit higher than the reference voltage of the next comparator. When an analog signal is input, those comparators whose wind reference voltage is lower than the analog signal all output high level (logic 1), otherwise they output low level (logic 0). The number thus obtained is called a thermometer code. This code is added to the decoding logic and then sent to the output register on the binary data output driver.

Although flash converters are extremely fast (up to 1GHz sampling rate), their resolution is limited by die size, excessive input capacitance, and the power consumption of a large number of comparators. Parallel comparators with repeated structures also require precise matching, so any mismatch will cause static errors, such as an increase in input offset voltage (or current).

Flicker-type ADCs are also prone to producing discrete, indeterminate outputs, so-called "flicker codes." There are two main sources of flash codes: the metastable state of the 2N-1 comparators and the thermometer encoding bubble; mismatched comparator delays can change logic 1 to logic 0 (or vice versa), as if a bubble appeared in the thermometer. Since the encoding unit in the analog-to-digital converter cannot recognize this error, the encoded output will also "flicker".

Another consideration for flash ADCs is die size. An 8-bit flash converter is nearly 7 times larger than a pipeline analog-to-digital converter with the same number of bits. If further comparison is made with the pipeline structure, the input capacitance and power consumption of the flash converter are 6 times and 2 times higher respectively.

1.4 Σ-Δ analog-to-digital converter

Σ-Δ converters are also called oversampling converters. This converter consists of a Σ-Δ modulator followed by a digital filter, as shown in Figure 4. The structure of the modulator is similar to a dual-slope analog-to-digital converter, including an integrator and a comparator, and a feedback loop containing a 1-bit analog-to-digital converter. The built-in digital-to-analog converter is simply a switch that switches the integrator input to a positive or negative reference voltage. The sigma-delta analog-to-digital converter also includes a clock unit to provide appropriate timing for the modulation and digital filters. The narrowband signal is fed into the Σ-Δ analog-to-digital converter and is quantized at a very low resolution (1 bit), but the sampling frequency is very high. After digital filtering, this oversampling is reduced to a lower sampling rate; at the same time, the resolution (i.e., dynamic range) of the analog-to-digital converter is increased to 16 bits or higher.

Although the sigma-delta analog-to-digital converter has a low sampling rate and is limited to a relatively narrow input bandwidth, it still occupies a very important position in the analog-to-digital converter market. It has three main advantages:

*Low price, high performance (high resolution);

*Integrated digital filtering;

*Compatible with DSP technology to facilitate system integration.

2 Pipeline analog-to-digital converter

From the above introduction to several commonly used analog-to-digital converters, it is not difficult to see that they all have shortcomings of one kind or another, and the pipeline structure (or called sub-area type) analog-to-digital converter is a more efficient and powerful analog-to-digital converter. digital converter. It can provide high-speed, high-resolution analog-to-digital conversion, and has satisfactory low power consumption and small chip size (meaning low price); after reasonable design, it can also provide excellent dynamic characteristics.

    The functional block diagram of the pipeline analog-to-digital converter is shown in Figure 5. The analog-to-digital converter of this structure uses multiple low-precision flicker-type analog-to-digital converter sampling signals for hierarchical quantization, and then combines the quantization results of each level to form a high-precision quantized output. Each stage consists of a sample/hold circuit (T/H), a low-resolution analog-to-digital converter and a digital-to-analog converter, and a summing circuit that also includes an interstage amplifier that provides gain. The procedure for an N-bit resolution pipeline analog-to-digital converter to complete a sampling is roughly as follows:

After the input signal of the sample/hold device of the first stage circuit is sampled, the input is first quantized by a coarse analog-to-digital converter with M-bit resolution, and then a product digital-to-analog converter (MDAC) with at least N-bit accuracy is used to generate a The analog level corresponding to the quantization result is sent to the summation circuit. The summation circuit subtracts this analog level from the input signal, and accurately amplifies the difference to a fixed gain before sending it to the next stage circuit for processing. After L-level processing, the residual signal is finally converted by a higher-precision K-bit fine analog-to-digital converter. The outputs of the above-mentioned coarse and fine A modules are combined to form a high-precision N-bit output. In order to facilitate the correction of overlap errors, redundant bits are left in circuits at all levels of the pipeline, that is, to satisfy:

L×M+K>N

Among them, L is the number of stages (varies among manufacturers), and M is the coarse resolution of the analog-to-digital converter circuit in each stage. K is the fine resolution of the fine analog-to-digital converter stage, and N is the total resolution of the pipeline analog-to-digital converter.

Each level of circuit in the pipeline analog-to-digital converter has its own track/hold circuit. Therefore, when the signal is passed to the secondary circuit, the track/hold of the current level circuit can be released to process the next sample. This improves the throughput of the entire circuit, and one sampling can be completed in one clock cycle. In order to compensate for undesirable boundary effects, such as temperature drift or capacitance mismatch in product-type digital-to-analog converters, some pipeline module converters are also equipped with correction units. This unit is usually used in multi-stage (but not all) circuits of the pipeline. It uses two correction codes to cause the product-type digital-to-analog converter to output a transition with an amplitude equal to VREF. Any deviation from this transition will be measured. The errors of the converters at each stage are collected and stored in the internal memory. During normal operation, the results are retrieved from the RAM and the gain of each link in the pipeline and the capacitance mismatch of the product digital-to-analog converter are compensated respectively.

In summary, the pipeline structure simplifies the design of analog-to-digital converters and has the following advantages:

*Redundant bits in each line optimize the correction of overlap errors;

*Each stage has its own independent sample/hold amplifier. The sample/hold amplifier of the previous stage circuit can be released to process the next sample, thus allowing each stage of the pipeline to process multiple samples at the same time;

*Lower power consumption;

*Higher sampling speed, lower price, less design time required and less difficulty;

*Very few comparators enter a metastable state, essentially eliminating flash code thermometer bubbles.

But at the same time, pipeline analog-to-digital converters also have some disadvantages:

*Complex reference circuit and bias structure;

*The input signal must pass through several levels of circuits, causing pipeline delays;

*Synchronizing all outputs requires strict latch timing;

* Sensitive to process defects, which will affect gain nonlinearity, offset and other parameters;

*More sensitive to PCB routing than other conversion technologies.

However, proper design of multilayer printed circuit boards can overcome many of the disadvantages mentioned above, and the selection of external components and the selection of an appropriate type of pipeline analog-to-digital converter (preferably including internal inter-stage gain and error mismatch calibration) can also improve the system. performance.

Conclusion

The development of analog-to-digital conversion technology is changing with each passing day, and pipeline analog-to-digital conversion technology is only one of the more excellent ones. It is believed that with the rapid development of digital technology and microelectronics technology, newer and better analog-to-digital conversion technology will surely emerge. Finally, I hope this article can provide some reference for readers when choosing a suitable analog-to-digital converter.