Abstract: PCM2702 is a 16-bit stereo digital-to-analog converter chip with USB interface recently launched by Burr-Brown Company. The article briefly analyzes the performance characteristics and working principle of the chip, and finally gives a typical application circuit of PCM2702.
1 Introduction
PCM2702 is a single-chip digital-to-analog conversion chip. It has two digital-to-analog conversion output channels and an integrated USB interface controller. This interface complies with USB1.0 standard. PCM2702 adopts the newly developed SPAct TM (Sampling Period Adaptive Control Tracking) system. The system can separate a stable, less-deviated clock signal from the audio data of the USB interface to coordinate the work of the PLL and DAC.
PCM2702 mainly consists of three parts: an enhanced multi-level delta-sigma modulator developed by Burr-Brown Company, an 8× repeated sampling digital interpolation filter, and an analog output low-pass filter.
PCM2702 can receive 16-bit stereo or mono audio data at 48kHz, 44kHz and 32kHz sampling rates. The chip integrates a software mute function with a digital potentiometer. The potentiometer and mute function can be controlled through USB audio level requirements.
2 Performance characteristics
2.1 Pin arrangement and functions
Figure 1 shows the pin arrangement of PCM2702, and Table 1 shows the pin function description.
Table 1 Pin function description
Pin | name | type | Function description |
1 | XTI | IN | Crystal oscillator input |
2 | VDDC | - | Clock generator power supply (3.3V) |
3 | DGNDC | - | clock generator digital ground |
4 | VDD | - | Digital power supply (3.3V) |
5 | DGND | - | digitally |
6 | D+ | IN/OUT | USB differential input/output positive |
7 | D- | IN/OUT | USB differential input/output negative |
8 | VBUS | IN | USB bus power (this pin absolutely does not consume USB bus power) |
9 | DGNDU | - | USB transceiver digital ground |
10 | PLYBCK | OUT | Playback indicator flag, active at low level (low level: playback; high level: waiting) |
11 | SSPND | OUT | Pause indicator flag, active at low level (low level: pause; high level, working) |
12 | ZERO | OUT | Low level is normal; high level is 0 |
13 | TEST3 | IN | Test pin 3, connected to digital ground |
14 | TEST2 | IN | Test pin 2, connected to digital ground |
15 | TEST1 | IN | Test pin 1, connected to digital ground |
16 | TEST0 | IN | Test pin 0, connected to digital ground |
17 | VCCR | - | Right channel analog power +5V |
18 | AGNDR | - | Right channel analog ground |
19 | VOUTR | OUT | Right channel analog output |
20 | AGND | - | Analogly |
twenty one | VCOM | - | Digital-to-analog converter (DAC) DC common-mode voltage |
twenty two | VCC | - | Analog power supply +5V |
twenty three | VOUTL | OUT | Left channel analog output |
twenty four | AGNDL | - | Left channel analog ground |
25 | VCCL | - | Left channel analog power +5V |
26 | AGNDP | - | Phase locked loop circuit analog ground |
27 | VCCP | - | Phase locked loop analog power supply +5V |
28 | XTO | OUT | Crystal oscillator output |
2.2 Performance characteristics
The main features of PCM2702 are as follows:
●With integrated USB interface. This USB interface fully complies with the USB1.0 standard, its full-speed data transmission rate can reach 12Mb/s, and it has a synchronous transmission adaptation mode and comes with its own power supply device.
●Can receive 16-bit stereo and mono USB audio data streams.
●Analog performance (Vcc=5V)
Dynamic range is 100dB;
Signal-to-noise ratio: 150dB (typical value);
THD+N: 0.002%;
Full scale output is 3.1Vp.
●With 8× repeated sampling digital filter.
●Sampling rate (fs) can be selected from 32kHz, 44.1kHz or 48kHz.
●Integrated independent 12MHz clock generator.
●With multimedia functions.
●Adopt dual power supply. The analog part is +5V; the digital part is +3.3V.
●Adopt SSOP-28 package form.
2.3 Electrical parameters
Table 2 lists the performance parameters of PCM2702. Unless otherwise specified, the parameters in the table are tested under the following conditions:
Table 2 Performance parameters of PCM2702
parameter | condition | PCM2702 | unit | ||||
minimum value | Typical value | maximum value | |||||
resolution | 16 | bits | |||||
host interface | Support USB1.0 version, full speed | ||||||
Digital signal | audio data mode | USB step output | |||||
Data bit length | 16 | ||||||
data channel | 1,2 | ||||||
Sampling rate (fs) | 32,44.1,48 | ||||||
Input logic level | V1H(1) | 2.0 | VDC | ||||
V1L(1) | 0.8 | VDC | |||||
V1H(2) | 0.7VDD | VDC | |||||
V1L(2) | 0.7VDD | VDC | |||||
Input logic current | I1H(1) | VIN=VDD | +65 | +100 | μA | ||
I1L(1) | VIN=0V | ±10 | μA | ||||
I1H(2) | VIN=VDD | ±10 | μA | ||||
I1H(2) | VIN=0V | ±10 | μA | ||||
Output logic level | VOH(3) | I0H=-1mA | 2.8 | VDC | |||
VOL(3) | I0L=+1mA | 0.5 | VDC | ||||
dynamic performance | THD+N(VOUT=0dB) | 0.002 | 0.005 | % | |||
THD+N(VOUT=-60dB) | 1.2 | % | |||||
Dynamic Range | EIAJ A-Weighted | 96 | 100 | dB | |||
signal-to-noise ratio | EIAJ A-Weighted | 100 | 105 | dB | |||
channel isolation | 98 | 103 | dB | ||||
DC accuracy | gain error | ±1.0 | ±3.0 | %FSR | |||
Gain mismatch between channels | ±1.0 | ±3.0 | %FSR | ||||
Zero point error of two poles | VOUT=0.5Vcc | ±30 | ±60 | mV | |||
Analog output | The output voltage | Full scale (-0dB) | 62%Vcc | Vp-p | |||
center voltage | 50%Vcc | VDC | |||||
Load impedance | 5 | kΩ |
TA=25℃, Vcc=VCCL=VCCR=VCCP=5.0V, VDD=VDDC=3.3V, fs=44.0MHz, signal frequency 1kHz, 16-bit data. Pins 8, 13, 14, 15, and 16 are VBUS, TEST3, TEST2, TEST1, and TEST0 respectively; pins 10, 11, 12, and 28 are PLYBCK, SSPND, ZERO, and XTO respectively.
The dynamic performance in the parameters is limited to the signal quality of the standard host and varies with different aspects of the system. The parameters of the dynamic performance are measured with a Shibasoku #725 THD measuring instrument. The instrument features a 400Hz high-pass filter, a 30kHz low-pass filter, a universal mode and a 20kHz bandwidth limit. The load on the analog output via the AC coupler is 5kΩ or greater.
3 Working principle
Figure 2 shows the block diagram of PCM2702. The working principles of each part are as follows:
3.1 USB interface
This USB interface complies with the Serial Shared Bus Revision 1.0 standard.
Both control signals and audio data signals are sent to the PCM2702 center through D+ (6 feet) and D- (7 feet). All data is input or output at full speed. The USB main power supply VBUS (pin 8) and the USB digital ground DGNDU (pin 9) are both connected to the USB bus. Since VBUS is only used to separate the connection between the chip and the USB bus, VBUS does not consume USB bus power. Table 3 is the relevant information of the USB interface.
Table 3 USB interface information
USB version | 1.0 |
0×00 (component determines the interface standard) | |
0×00 (no specification) | |
0×00 (no specification) | |
Maximum data length of terminal O | 8 bits |
0×08BB | |
Chip identification number | 0×2702 |
Version | 1.0 |
3.2 Component structure
Figure 3 is the USB audio function logic block diagram. PCM2702 has two interfaces, each of which consists of some optional settings. Interface #0 has an alternative setup. Alternative setup #0 is a standard audio control interface and has one port. PCM2702 has the following three ports, input port (IT), output port (OT) and functional unit (FU). The input port is defined as a "USB" data stream (port type 0×0101). The input port can receive two channels of audio streams. These two channels can be used as compressed data transmission channels for the left and right channels of the audio stream respectively. The output port is the "speaker" port (port type 0×0301.)
The function control unit supports volume control and mute control functions. The built-in digital volume control potentiometer can be adjusted between 0.0dB and 64.0dB in steps of 1.0dB according to the specific requirements of the audio level. Each channel can be set independently and also supports master volume control. The built-in digital mute controller can also be operated according to the specific requirements of the audio level to support master mute control, but does not support individual channel adjustment control.
Interface #1 has 3 selectable settings: Alternate setting #0 is the zero bandwidth setting; Setting #1 is the 16-bit stereo setting, which is an operational setting; Setting #2 is the 16-bit mono setting, which is also An operability setting. PCM2702 has two terminals, namely: control terminal (EP#0) and synchronous audio data stream terminal (EP#2). The control terminal is the default terminal and is commonly used to control all functions of the PCM2702 according to standard USB requirements and the specific requirements of the USB audio level. The isochronous audio stream terminal is an audio absorbing terminal that receives the audio stream from the PCM and receives the reconfigured transmission mode.
3.3 Clock and reset circuit
PCM2702 requires a 12MHz (±500ppm) clock to coordinate the work of the USB and audio function control sections. The clock signal can be provided by the internal integrated 12MHz crystal oscillator, or the 12MHz internal clock signal can be input to XTI (pin 1) (as shown in Figure 4). The 12MHx crystal resonator is connected to XTI and XTO, the capacitance value depends on the load of the specific crystal resonator. If the internal clock is used, it should be input from XTI, and XTO must be left floating. The logic level of the XTI pin clock signal is +3.3V, not 5V. Figure 5 is the external 12MHz clock connection circuit.
The PCM2702 contains an internal power-on recovery circuit. When the VDD level is greater than 2.0V, the circuit will automatically restore the starting digital logic level, and the whole process takes about 350μs. To ensure the normal operation of the power-on sequence, the VDD voltage must rise to 2.0V within 10ms.
3.4 Interface timing
● Power on, connection and playback timing
When the circuit completes the recovery of the starting level and the USB bus is turned on, the PCM2702 setting is ready. When the connection to the USB bus is established, the PCM2702 is ready to receive USB audio data. While waiting for audio data to be sent, the analog output is set to the double zero point zero mark, and ZERO (pin 12) is high level.
After receiving the audio data, PCM2702 stores the first batch of data packets (including 1ms audio data) into an internal memory. When the first frame is detected, PCM2702 starts playback.
●Playback stop and separation timing
When the host completes or stops audio playback, the PCM will stop playback after receiving the last transmitted audio data. The playback stop and separation timing of PCM2702 is shown in Figure 6.
3.5 PLYBCK, SSPND and ZERO marks
The PLYBCK, SSPND and ZERO flags are defined as follows:
PLYBCK: When PCM audio input data is being played, PLYBCK (pin 10) is low-level active;
SSPND: When the USB interface is in the suspend state, SSPND (pin 11) is active at low level.
ZERO: If the PCM audio input data continues to be 0 for 102 sampling periods, it enters the ZERO state. ZERO (pin 12) is active at high level.
4 applications
PCM2702 can be used in various USB audio devices such as standard independent USB audio speakers, CRT/LCD integrated USB audio field speakers, USB audio amplifiers, etc. Figure 7 shows a typical application circuit of PCM2702.
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