Design of 8-channel parallel data acquisition PCI module

Design of 8-channel parallel data acquisition PCI module

Data acquisition is one of the main functions of automatic test systems. In some application areas, such as ultrasound and medical electronics, different frequency ranges of signals require different sampling rates. Sometimes, in order to cooperate with signal processing algorithms, the sampling rate is even required to be set arbitrarily within a certain range. Moreover, these applications usually require parallel acquisition of multiple channels, or even differential single-ended selectable inputs. In response to these requirements, we propose a synchronous parallel multi-channel data acquisition solution with up to 12 channels. The solution can achieve a maximum sampling rate of 10MS/s, a storage depth of 2×32M×16bit (2 SDRAMs), a vertical resolution of 14bit, and programmable gain of 1, 2, 5, 10, and 100.

Determination of the design scheme
The hardware circuit mainly includes signal conditioning circuit, signal input mode selection circuit, programmable gain circuit, A/D conversion, data storage, trigger control and PCI interface. After the analog signals input from 8 channels are conditioned by the signal conditioning circuit, they are converted from single-ended to differential (the front end can also be 8-channel differential signals directly input). After the input mode is selected by the multi-way switch, the gain is controlled by a two-stage selectable gain amplifier, and finally enters the ADC to convert into the corresponding digital signal. After receiving the acquisition command, the logic control unit will start the ADC for sampling according to the corresponding trigger mode, and then store the sampled data in SDRAM through the internal serial-to-parallel conversion logic and data output arbitration logic of the FPGA for upload. The acquisition limit indicator of this design is simultaneous acquisition of 8 channels, the maximum sampling rate is 10MS/s for a single channel, and the maximum continuous sampling storage time can reach 3.2s. The host computer uses the query, interrupt or DMA method through the 32-bit data bus to read the collected data into the memory for later data processing and analysis. The basic structure of the system is shown in Figure 1.

Figure 1 System block diagram

Figure 2 Signal input mode selection circuit

Signal conditioning circuit design
In this design, the signal conditioning circuit includes an input mode selection circuit and a gain selection circuit. In this part, the voltage follower composed of a common operational amplifier with high input impedance and low output impedance will isolate the front and rear circuits to prevent the on-resistance of the rear-stage multi-way switch from affecting the front-stage circuit. Two diodes are added to the input end to provide a ±15V clamping voltage to form overvoltage protection. The multi-way switch selects DG409, which is a 4-channel differential multi-way switch with low on-resistance, low power consumption and low leakage current. There are four signal input modes: 0 input, single-ended positive input, single-ended negative input and differential input. These four input modes can be selected through DG409. The circuit is shown in Figure 2.

After selecting an input mode, through the two-stage programmable gain instrumentation amplifier AD8250, the gain value can be selected to five levels: 1, 2, 5, 10, and 100. AD8250 has two gain control terminals A0 and A1. Writing these two bits can select the gain value and latch the state value through W/R to ensure the stability of the gain. This design writes data into CPLD by designing serial transmission logic inside FPGA, and then controls the input mode of the selection signal and writes the AD8250 gain control bit. The gain selection circuit is shown in Figure 3.

Figure 3 Gain selection circuit

Data acquisition and control circuit design
A/D converter is the core of the data acquisition system, and the selection of A/D devices often affects the performance indicators of the entire system. In order to achieve 8-channel parallel synchronous sampling, two solutions can be adopted. One is to use 8 independent A/D converters, which is not only costly, but also difficult to achieve 8-channel synchronous sampling, and there are also great difficulties when drawing PCB boards. The second way is the method of this design, using an AD9252 to meet the parallel synchronous sampling requirements of up to 8 channels. This design sends a control word to AD9252 through the NIOSII soft-core processor to achieve 8-channel parallel synchronous sampling. First, output 14-bit LVDS signal to FPGA, output 14-bit parallel data through serial-to-parallel conversion logic, and then realize different data storage locations of different channels through arbitration logic. Finally, continuous data acquisition and transmission are achieved through the ping-pong operation of two SDRAMs.

The digital control part of this design is completed by the cooperation of FPGA and external CPLD. Since the design requires a large number of pin resources, and the pin resources of FPGA are limited, a CPLD is connected to the outside of FPGA through the SPI bus interface to control the input mode selection and gain selection of 8 channels. A NIOSII soft core is embedded in the FPGA, which is responsible for data acquisition, data transmission, input mode and gain selection control. The following is a detailed analysis of the implementation methods of these three digital control circuits.

1. Implementation of signal input mode and gain selection control logic
FPGA and CPLD communicate via serial bus. An 8-bit address bus and 8-bit data line RAM block are built inside the FPGA to store input mode and gain selection control data. The first three bits of the 8-bit address line are used to control the channel number, and the last five bits control the 20 selection states of the channel (4 input modes, 5 gain selections). The first two bits of the 8-bit data are the input mode selection code, and the last six bits are the gain selection code. An address counter is built inside the FPGA to extract the channel selection data. The clock frequency of the counter is 32 times that of the SPI controller clock.

A 48-bit serial-to-parallel conversion logic is constructed in the CPLD, and the input mode selection code and gain selection code are sent to the corresponding pins, thereby realizing the implementation of the signal input mode and gain selection control logic.
2 Implementation of data acquisition and transmission control logic
The design logic of this design in the FPGA is as follows:
● Read the ADC serial LVDS data stream, and then convert the serial data stream into a parallel data stream through the serial-to-parallel conversion logic;
● Internally design the SDRAM control logic to realize data storage, and realize the data storage of different channels in SDRAM according to a certain timing through the internal arbitration logic;
● After judging that the first SDRAM is full, the data is stored in the second memory through the chip select switching logic, and the data is transmitted to the host computer through DMA.

Figure 4 Control logic block diagram

Figure 4 is a block diagram of the internal control logic of the FPGA.

3 PCI interface circuit design

This design uses the PCI bus as the data bus to connect the acquisition module and the host computer for communication, in order to realize functions such as data analysis and processing and historical display.

Since the acquisition module in the design needs to work in a continuous acquisition system, when the memory is full, a fast output channel is required to transmit the data through the PCI interface. This design uses DMA to transmit data, which not only does not occupy CPU resources, but also achieves fast data transmission. We chose the relatively stable dedicated PCI interface chip PCI9054 as the bus controller to communicate with the host computer. The chip complies with the PCI2.2 bus specification and supports low-cost slave adapters. The PCI clock is 0~33MHz, the theoretical data transmission rate can reach 132Mb/s, and the actual rate is 60Mb/s.

Figure 5 PCI interface circuit

In this design, PCI9054 is configured as slave mode, and FPGA is used as the master controller to realize data transmission control. PCI9054 has three bus operation modes: M mode, C mode and J mode. M mode is mainly used with MPC850/MPC860 processors, mainly used in the telecommunications field. J mode is used to meet the situation where the interface design is more complex, and C mode is mainly a general mode. This design adopts C mode, and the interface circuit is shown in Figure 5.

FPGA designs the read-write control logic according to the read-write timing of PCI9054, receives the command from the host computer, sets the circuit accordingly, starts ADC to collect data, and then sends the collected data to SDRAM; when an SDRAM is full, an interrupt is generated, and the address line of the full SDRAM is mapped to the local data line of PCI9054. At the same time, the DMA controller of PCI9054 is configured through the local master control mode, and the prepared data in SDRAM is uploaded through DMA. This design uses a 14-bit local data bus and a 24-bit address bus for data transmission and address decoding control.

Conclusion
By fully considering various factors that may affect signal quality in the design, an overvoltage protection circuit is designed. By selecting appropriate components, the complexity of circuit board design is reduced, and the cost is optimized. After actual testing, the module has well met the technical indicators mentioned in this article and is highly practical.