Encoding system based on STM32F103RET6

Introduction

Manchester encoding is widely used in Ethernet, vehicle bus, and industrial bus because of its characteristics of no DC component during transmission and convenient clock extraction. The commonly used Manchester encoding chips in engineering are HD-6408 and HD-6409, but this chip has some shortcomings. First, the chip has strict restrictions on the transmission rate and the number of effective bits in each frame of data. Secondly, the use of this chip requires additional hardware circuits, which increases the system cost. Using FPGA for Manchester encoding is costly and has a long development cycle. This paper proposes a coding system solution based on STM32F103RET6, which utilizes the powerful timer function of STM32F103RET6 and adopts a flexible coding method. The transmission rate and data frame format can be completely defined according to needs. The built-in DMA function of STM32F103RET6 makes data encoding no longer require frequent timer interrupts, improves the encoding rate, and saves CPU resources. The implementation method of this design is simple, stable, flexible, and has a wide range of applications.

1 Manchester code

Manchester code is an automatic synchronization encoding method, that is, the clock synchronization signal is hidden in the data waveform. In Manchester code, there is a jump in the middle of each bit, and the jump in the middle of the bit serves as both a clock signal and a data signal. Each code element is represented by two level signals with different phases. Compared with non-return-to-zero binary codes represented by high and low levels, it is easier to extract synchronization clock information in the case of continuous "0" or continuous "1". In addition, Manchester code has no DC component during transmission, which can reduce the power consumption of the system and has strong anti-interference ability. Figure 1 shows the most commonly used Manchester encoding method. When the transmitted signal is "1", Manchester code jumps from high level to low level; if the transmitted information is "0", Manchester jumps from low level to high level. Maintaining a low level without jumps within a data cycle indicates idle.

Figure 1 Manchester code

2 Introduction to the timer and DMA of STM32F103RET6

The controller uses ST's STM32 microprocessor. The STM32 series microprocessor is based on the ARM Cortex-M3 core and uses an efficient Harvard structure three-stage pipeline to achieve 1.25DMIPS/MHz. Here we use the enhanced STM32F103RET6. It has the following features: 72 MHz system clock frequency, 512 KB flash program memory, 64 KBSRAM, 8 timers, 3 12-bit analog-to-digital converters, 1 digital-to-analog converter, 1 CAN interface, 7-channel DMA controller, and SPI, USART, I2C, I2S, USB interface, etc. The controller has rich peripherals and strong anti-interference ability, and is very suitable for industrial field control.

STM32F103RET6 has 8 timers, each of which consists of a 16-bit auto-load counter with programmable pre-scaling. The counting frequency is up to 72 MHz. It is suitable for a variety of occasions including the pulse length of the input signal (input capture) or the generation of output waveforms (output comparison or PWM).

STM32F103RET6 supports DMA operation. DMA is a high-speed data transmission channel between the external and the memory or between the memory and the memory. Through DMA, data can be moved quickly without the participation of the CPU, which saves CPU resources to do other things. This design uses the counter to trigger DMA to exchange data between the memory and the timer, which improves the efficiency and stability of the encoding compared to the interrupt query method.

The maximum counting frequency of the timer is 72 MHz, and the DMA transmission rate is 6 Mb/s, so the Manchester encoding rate can easily reach 1 Mb/s, meeting the needs of high-speed encoding.

3 System Implementation Scheme

The block diagram of the Manchester voltage and current encoding and decoding system based on STM32F103RET6 is shown in Figure 2. This system design mainly uses the timer plus DMA function of the STM32F103RET6 chip to implement Manchester voltage encoding and decoding. For current encoding and decoding, it is necessary to use the peripheral voltage and current conversion circuit to implement it.

Figure 2 Block diagram of Manchester voltage and current encoding and decoding system based on STM32F103RET6

3.1 Voltage encoding

Set the timer to the output comparison flip function, apply for a buffer area, and convert the data to be encoded into a flip match value through the encoding algorithm and put it into this buffer area, as shown in Figure 3. The ABC DEF... count value, the encoding algorithm is written according to the encoding protocol in the specific application. After starting the timer, the counter starts counting. When the count value matches the value of the timer compare register, the level of the output pin flips and triggers DMA to update the compare register from the buffer area; each time it is updated, the memory address pointed to by DMA increases by 1, pointing to the data to be updated to the compare register next time, so that the timer outputs the corresponding encoding waveform according to the data in the buffer area. The encoding rate can be adjusted by modifying the timer prescaler and RCC clock controller divider.

Figure 3 Edit Example

3.2 Voltage Decoding

Set the timer to the input capture function. When the rising or falling edge of the Manchester code arrives, the timer will capture the current count value and transfer it to the buffer via the DMA channel; the main program will call the decoding algorithm to process and decode the data in the buffer. Decoding is the inverse process of encoding, and its decoding algorithm should also be written according to the encoding protocol in the specific application.

3. 3 Current Coding

The voltage coding is realized by the voltage/current conversion circuit shown in Figure 4, and the Manchester voltage code output by the timer is converted into the Manchester current code.

Figure 4 Voltage/current conversion circuit

3.4 Current decoding

The Manchester current code signal to be measured is converted into a voltage code through current/voltage, shaped to make the edge steeper, and then handed over to the MCU for decoding. The current/voltage conversion circuit is shown in Figure 5.

Figure 5 Current/voltage conversion circuit

4 Software Design

The software flow is shown in Figure 6. System initialization includes clock initialization, timer initialization, DMA initialization, etc. If the data to be encoded continuously at one time is relatively large, the DMA buffer should be set as double buffer, and two buffers should be opened for each DMA channel used. When DMA uses one of the buffers, the MCU calls the encoding or decoding algorithm to read and write to the other buffer; when the DMA data is transmitted, a DMA transmission end interrupt occurs, and the interrupt service program switches to another buffer, and the encoding algorithm or decoding algorithm flag is set. When the main program queries the flag position, the MCU calls the encoding or decoding algorithm to process the buffer previously pointed to by DMA (fill data or fetch data). Of course, if the data to be encoded or decoded at one time is not much, we only need one buffer.

Because the CPU processes data faster than the encoding rate, the CPU can spare time to do other things. The length of time depends on the size of the buffer and the encoding rate. Wait until the encoding or decoding flag is queried in the main program before executing the encoding or decoding algorithm to process the data, which improves the CPU's work efficiency. In applications with low real-time requirements, a dedicated CPU is no longer needed to process encoding or decoding.

5 Solution Verification

This solution has been verified in the automotive acceleration sensor simulation system. Here, the Manchester encoding protocol of a certain acceleration sensor is taken as an example. Its data frame format is a frame of 19 bits including: 2 start bits, 2 category bits, 10 data bits, and 5 CRC validation bits.