Using P110C to control 6 DC motors simultaneously

In the figure below, the six PWM output ports (PWMO-PWM5) of PLLOC are used to drive six Darlington transistors, which in turn drive the motor (Ml-M6). The purpose of speed regulation is achieved by setting the duty cycle of the PWM output pulse. The smaller the PWM duty cycle, the lower the motor drive voltage and the lower the speed; the larger the PWM duty cycle, the higher the motor drive voltage and the higher the speed. The duty cycle setting value ranges from 000 to 255, and the duty cycle changes by 0.392157% for each change in a number. Taking the reverse polarity output as an example, when the setting value is 000, the duty cycle is 0% and the output voltage is 0; when the setting value is 128, the duty cycle is 50%, and the output voltage is half of the supply voltage; when the setting value is 255, the duty cycle is 100%, and the output voltage is the highest.

The following introduces the program by taking the control of M1 motor as an example.

Example:
CWFl=3 (set the frequency of the P/F clock generator to: 245Hz)
PWM2=ON:O (activate PWM, set PWM to reverse polarity output)
PWM2=128 (set PWM output duty cycle to 50%)