s3c2410 interrupt handler

s3c2410 interrupt program
It is important to distinguish between the interrupt vector table and the exception vector table. After an interrupt occurs, it always enters from the IRQ or FIQ exception entry, and then jumps to the corresponding exception handler for execution. This exception handler generally searches for the interrupt vector table and then calls the interrupt handler.
The following is the process of implementing interrupt handling in the application: It is not difficult to understand the interrupt handling process.
Define the physical address of the interrupt vector table:
code.equ
pISR_DABORT, (_ISR_STARTADDRESS+0x10)
.equ pISR_RESERVED, (_ISR_STARTADDRESS+0x14)
.equ pISR_IRQ, (_ISR_STARTADDRESS+0x18)
.equ pISR_FIQ, (_ISR_STARTADDRESS+0x1c) //Exception vector table
………………………………………………………………
.equ pISR_EINT0, (_ISR_STARTADDRESS+0x20) //Interrupt vector table.equ
pISR_EINT1, (_ISR_STARTADDRESS+0x24)
.equ pISR_EINT2, (_ISR_STARTADDRESS+0x28)
.equ pISR_EINT3, (_ISR_STARTADDRESS+0x2c)
Put the interrupt handler entry address into the interrupt vector table:
code
pISR_EINT0 = (unsigned int)isrEINT0; // isrEINT0 interrupt handler
pISR_EINT1 = (unsigned int)isrEINT1;
Define the interrupt handler:
code
.extern Interrupt_Rbutton
.global isrEINT0
isrEINT0:
IRQHandle Interrupt_Rbutton
Define the exception vector table:
code
b HandlerUndef /* handler for Undefined mode */
b HandlerSWI /* handler for SWI interrupt */
b HandlerPabort /* handler for PAbort */
b HandlerDabort /* handler for DAbort */
.long FileIDTable /* id */
b HandlerIRQ /* handler for IRQ interrupt */
b HandlerFIQ
Define the exception handling function:
code
HandlerFIQ: HANDLER HandleFIQ
HandlerIRQ: HANDLER HandleIRQ
HandlerUndef: HANDLER HandleUndef
HandlerSWI:
HANDLER HandleSWI HandlerDabort: HANDLER HandleDabort
HandlerPabort: HANDLER HandlePabortException
handling macro HANDLER definition:
code.macro
HANDLER HandleLabel
sub sp,sp,#4 /* decrement sp(to store jump address) */
stmfd sp!,{r0} /* PUSH the work register to stack(lr does't push bec
ause it return to original address) */
ldr r0,=HandleLabel /* ​​load the address of HandleXXX to r0 */
ldr r0,[r0] /* load the contents(service routine start address) of
HandleXXX */
str r0,[sp,#4] /* store the contents(ISR) of HandleXXX to stack */
ldmfd sp!,{r0,pc} /* POP the work register and pc(jump to ISR) */
.endm
define IRQ interrupt handling macro IRQHandle:
code
.macro IRQHandle isrHandle:
stmdb sp!, {r0-r11, ip, lr} /* save r0-r11, ip, lr */
ldr r0, =isrHandle
mov lr, pc
bx r0 /* jump to user_handle(void) */
ldmia sp!, {r0-r11, ip, lr} /* restore r0, ip, lr */
subs pc, r14, #4 /* return from interrupt */
.endm
declares that the service routine for IRQ exception is: IsrIRQ, that is, when an IRQ exception occurs, execute "b HandlerIRQ", that is,
run IsrIRQ code:
code
ldr r0,=HandleIRQ @ This routine is needed
ldr r1,=IsrIRQ @ if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
IRQ exception handler:
code
IsrIRQ:
sub sp,sp,#4 @ reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,[r9]
ldr r8,=HandleEINT0
add r8,r8,r9,lsl #2
ldr r8,[r8]
str r8,[sp,#8]
ldmfd sp!,{r8-r9,pc}
In embedded systems, the exception vector table and interrupt vector table are stored in a space at the beginning of FLASH. The exception handling and interrupt handling programs are both running in RAM.

From the above, we can know that when an IRQ interrupt occurs, the CPU will fetch instructions from 0X18 (IRQ exception entry address) and execute. At this step, the jump of the PC is implemented by hardware. A jump instruction is placed at the entry address 0x18. This instruction will jump to the IRQ exception handler. The IRQ exception handler mainly searches the interrupt vector table according to the interrupt source. After obtaining the interrupt entry address, the CPU then jumps to the interrupt handler.