Design of protection scheme for high frequency data transmission interface circuit

Design of protection scheme for high frequency data transmission interface circuit

The continuous development of IC process technology and the popularity of high-speed data transmission interfaces have made related ESD protection increasingly difficult. The strong demand for faster processing speeds and higher functional density has pushed IC manufacturers to further reduce the minimum size of MOS components. Especially when the manufacturing technology turns to below 90nm, IC chips are getting smaller and smaller, with higher density and more complex functions, while the electromagnetic environment in which they are used is becoming increasingly harsh, making them more susceptible to damage from ESD, overvoltage and overcurrent. At the same time, the continuous development of various high-speed interfaces, especially the rapid growth of portable multimedia devices, has made high-speed data transmission inevitable. How to ensure high-speed data transmission while protecting the security of the interface has become a difficult problem faced by high-frequency data interfaces.

Circuit protection requirements for different interfaces

Among the current mainstream interfaces, USB is the most widely used, and the latest USB3.0 will support a transmission speed of up to 5Gbps. When the transmission speed is increased to such a high speed, the signal retention time is only 200ps. At this time, traditional high-capacitance MLV, TVS and other devices will not be able to be used for ESD protection, and high parasitic capacitance will seriously cause signal waveform distortion: it reduces the level retention time, greatly changes the rising and falling edges of the signal, so that the signal cannot reach the normal working level. In comparison, the HDMI1.3 standard doubles the data transmission rate of the early HDMI1.0-1.2 to 3.4Gbps per pair of differential signals. To achieve such a high data transmission rate, low capacitance and excellent circuit board design will become the key to fully ensure signal integrity.

The new DisplayPort interface is also being adopted by many personal computers, monitors, projectors and other display content (playback) source designs. The DisplayPort interface operates at a rate of up to 2.7Gbps, which is much higher than the original video/multimedia interconnection standard, and therefore faces the same challenges. Hard disk drive, computer and set-top box manufacturers are aligning with the E-SATA (external serial ATA) standard as a fast way to transfer video between storage devices. The latest SATA3.0 standard newly defines a maximum transmission bandwidth of up to 6Gbps. The ESD requirements of E-SATA technology are very similar to those of HDMI and DisplayPort. The hot-swappable nature of E-SATA makes high-level ESD protection particularly critical.

Figure 1. Comparison of signal speed requirements for different high-speed interfaces

It can be seen that for designers, the complexity and difficulty of high-speed interface circuit protection design comes from the working speed. Many designers feel at a loss as to how to use various speed expressions.

Taking HDMI1.3 and DisplayPort as examples, HDMI1.3 generally refers to working at a data transmission speed of up to 10Gbps at 340Mpixel/s. The maximum transmission speed here means that the interface will change its clock rate according to the video capabilities of the connected generator and receiver. The higher the resolution or color depth of the two connected devices, the higher the clock frequency. For example, high-definition video in 1,080p mode has more data information to process than in 1,080i mode, and the clock rate is also faster. In actual operation, the operating speed of HDMI depends on the capabilities of the transmitter and receiver as well as the resolution and color depth of the playback source. Figure 1 shows the maximum operating rate of TMDS, a commonly used high-speed interface.

The DisplayPort standard specifies two operating speeds: 1.62GHz and 2.7GHz. Designers can choose the lower operating speed based on specific usage and cost factors, while the higher speed can enable faster refresh rates, higher resolutions, and richer color depth.

In some cases, it is possible to implement a design with two speeds. The latest USB 3.0 specification greatly increases the need for low capacitance ESD devices. USB 3.0 adds two high-speed differential signal pairs to the existing USB 2.0. Since the transmit and receive differential signal pairs can operate at up to 5GHz, USB 3.0 requires signaling that is 50% faster than DisplayPort. At these speeds, any additional capacitance will affect the eye diagram and thus affect compliance with the USB 3.0 specification.

The main difficulty in protecting the above high-speed data transmission interface circuit is that the excessive parasitic capacitance of the protection device will cause a certain degree of signal attenuation, thereby reducing the display quality. Therefore, ESD devices should be selected according to the signal frequency of the circuit interface they protect, with sufficiently low capacitance and stable ESD shunt capability, and trade-offs should be made between component size, ESD protection performance, and ease of implementation. When adding ESD protection to high-speed data interface circuits, the timing effects of added capacitance and inductance on high-speed differential signals must be considered. When USB3.0 operates at speeds up to 5GHz, any additional impedance on the line may distort the signal, making it difficult to meet the signal rise time and maintain the signal level in the specified eye diagram.

Choosing the right ESD protection device

The timing performance of high-speed signals is generally measured using an eye diagram, an analytical tool used to accurately display timing and comment on errors. As shown in Figure 2, the gray portion in the middle of the eye diagram represents the electrical specifications of the high-speed differential signal. As the lines gradually encroach on the gray portion, the error margin becomes smaller and smaller. The eye width is an ideal indicator of the data line settling time and whether there is an error. The eye height indicates the signal level or amplitude. Since the TMDS pair is a differential signal, it is very important to minimize the differential capacitance and signal-to-ground capacitance to ensure that the signal rise time and fall time meet the requirements. Ideally, the capacitance is low enough to give the designer enough design margin.

Figure 2 Eye diagram of a 0.25pF PESD device from Tyco Electronics operating at 3.4GHz

In order to meet the requirements of high-speed data communication interfaces, effective ESD protection without affecting high-speed signal transmission. In recent years, a variety of devices specifically suitable for such protection requirements have been launched on the market, such as the polymer ESD suppression device PESD launched by the Raychem Circuit Protection Division of Tyco Electronics, and the low-capacitance silicon ESD device SESD. The capacitance of PESD devices is extremely low, with a typical value of 0.25pF, and a very small leakage current (<0.001A); ESD protection is fast and effective, and the price is lower than that of low-capacitance silicon devices. The low-capacitance silicon ESD devices launched by Tyco Electronics include SESD0201C-006-058 with a typical capacitance of 0.6pF in 0201 package, and SESD0402S-005-054 with a typical capacitance of 0.5pF in 0402 package.

Figure 2 shows the eye diagram performance of Tyco Electronics' 0.25pF PESD device operating at 3.4GHz (HDMI 1.3). As shown in the figure, when the interface transmission speed is as high as the highest 3.4GHz defined by HDMI1.3, the signal using Tyco Electronics' PESD electrostatic protection component has sufficient margin in the signal rise time, fall time and signal level during transmission, which can ensure that normal data transmission is not affected.

Low insertion loss and stable capacitance covering a wide frequency range also have an important impact on achieving the ultimate goal of adequate protection, cost savings and minimal signal attenuation. Insertion loss is an important indicator to measure the relationship between signal attenuation and frequency. Excessive insertion loss will reduce device and system bandwidth and bring additional design constraints to meet the eye diagram level.

The capacitance and frequency characteristics of ESD protection devices may also affect the design performance of high-speed ports, thereby increasing design constraints. In high-speed systems, circuits designed for a specific capacitance may perform differently depending on the ESD protection method used, forcing designers to use complex software process improvement and capability measurement (SPICE) models and simulation methods when conceiving HDMI circuit protection mechanisms. Figures 3 and 4 show the insertion loss of two ESD devices used by Tyco Electronics for high-speed data transmission interface protection at high-frequency transmission rates.

Figure 3 Insertion loss curve of TE Connectivity Raychem PESD device

Figure 4 Insertion loss curve of TE Connectivity Raychem SESD device

Compared with other polymer ESD protection devices, PESD of Tyco Electronics has the characteristics of lower trigger voltage and clamping voltage, tolerance to ESD shock, and long life; SESD has a slightly higher capacitance (0.6pF) than polymer PESD components, but its trigger voltage and clamping voltage are relatively lower, which has a better protection effect on extremely sensitive ICs. The two products launched by Tyco Electronics can fully cover the protection of high-speed data transmission interfaces. Designers can choose according to the protection level, operating frequency of the interface circuit, component size, cost, and convenience of implementation. These two series of products use the most popular 0603, 0402 and the smallest 0201 packages in the electronics industry, meet the strict requirements of RoHS, and can help set-top box sensitive circuits, laptops, mobile phones and other portable devices avoid ESD damage.

PPTC overcurrent protection

For safety and regulatory reasons, the HDMI, USB, and DisplayPort specifications also require overcurrent protection for end-user accessible power connectors. Overcurrent protection devices must be resettable without mechanical user intervention, and their preset operating limits must be higher than the allowed transient current to prevent false operation. At the same time, the normal resistance of the protection element must be low enough to avoid causing too much voltage drop. Polymeric positive temperature coefficient (PPTC) devices have proven their effectiveness in various high-speed interface applications. Like traditional fuses, they limit loop current when the current exceeds the specified limit current. However, unlike fuses, PPTCs can be reset after the fault is cleared and the power supply is re-applied. PPTC devices have the characteristics of low resistance, fast operating time, and small size, making them the preferred method of overcurrent protection in many power bus architectures.

Unlike HDMI and DisplayPort, USB interfaces are usually used to provide power and charging functions for portable electronic products. Therefore, downstream devices powered or charged by USB interfaces are subject to damage caused by inductive voltage spikes, incorrect chargers, and reverse bias. Tyco Electronics' polyZen component is a polymer-protected precision Zener diode micro-integrated module, which is composed of a stable Zener diode with precise clamping voltage and a nonlinear polymer PTC (positive temperature coefficient). The PTC responds to diode overheating or overcurrent faults by switching from a low-resistance state to a high-resistance state. The PolyZen component has the characteristics of resettable protection against high-power fault events, while only 0.7W of power consumption. When the diode overheats or overcurrent occurs, the PTC "acts" to limit the current and generate a voltage drop, helping to protect the Zener diode and the electronic equipment behind it, thereby effectively improving the power handling capability of the diode.

Figures 5, 6 and 7 show the schematic diagrams of HDMI1.3, USB3.0 and Display port interface protection circuits designed using Tyco Electronics ESD devices, MLV devices, PolySwitch overcurrent protection devices, and PolyZen overcurrent and overvoltage protection devices.

Figure 5 Typical HDMI interface circuit protection scheme design - ESD and overcurrent protection

Figure 6 Typical DisplayPort interface circuit protection scheme design - ESD and overcurrent protection

Figure 7 Typical USB 3.0 circuit protection design - ESD, overcurrent and overvoltage protection