Intermediate Frequency Digitization of Shortwave Communication Based on Software Radio

introduction

The purpose of software radio technology is to construct an open, standardized, and modular universal hardware platform, which uses software to complete various wireless communication functions, such as working frequency band, modulation and demodulation type, data format, encryption and anti-interference mode, communication protocol, etc., and to make broadband A/D and D/A converters as close to the antenna as possible. The ideal software radio structure is shown in Figure 1. Among them, N-/RT stands for punctual and real-time; the source/destination includes narrowband services and future broadband services.

Traditional shortwave radio stations are only suitable for transmitting analog voice and low-rate data due to the crowded frequency resources, severe frequency selective fading of time-varying ionospheric channels, multipath delay, various atmospheric noises and artificial radio noise. With the development of modern wireless communication theory and software and hardware technology and the in-depth exploration of ionospheric channel characteristics, shortwave radio stations have undergone the following changes: ① frequency hopping technology is used to improve anti-interference capabilities; ② adaptive communication technology is used to improve link building capabilities; ③ data communication (including graphic data and voice coded data, etc.) has become an important service mode; ④ digital encryption methods are used, etc.

Theoretically, the current ADC speed can meet the requirements of low-pass sampling of shortwave band signals, but there are the following problems when performing A/D conversion directly at the RF end. ① It seriously affects the selectivity and sensitivity of the receiver. Generally, there will be several strong narrowband interferences in the RF band. In order to prevent overload and reduce the quantization noise of the ADC, the ADC must have a large dynamic range. When the signal is very weak and close to the noise floor, the spurious-free dynamic range SFDR index of the ADC determines the total SNR of the receiver, and the implementation of the ADC is very difficult; ② The shortwave band bandwidth is relatively wide, and the performance of the broadband anti-aliasing filter and broadband amplifier before the ADC is not ideal at present; ③ It is very difficult for the digital signal processor to perform channel separation and demodulation of the narrowband signal in the RF band; ④ The signal-to-noise ratio deterioration caused by the ADC sampling aperture jitter is relatively serious. Therefore, the current digital transformation of traditional shortwave radio stations mostly retains the radio frequency and analog mixing links of the radio station, and is carried out at a lower and fixed second intermediate frequency.

The shortwave intermediate frequency digital platform designed in this paper is digitized at the second intermediate frequency 500kHz, thereby eliminating a series of analog demodulation links such as sideband filtering of traditional radio stations, and building a unified hardware platform to realize software modulation and demodulation of single sideband, amplitude modulation, and constant amplitude voice, and on this basis, load frequency hopping, adaptive, parallel and serial modem data transmission and other modulation and demodulation modules. The structural principle of the shortwave intermediate frequency digital platform is shown in Figure 2. Among them, N-RT is quasi-real time and real time; the source/destination includes narrowband services and future broadband services.

1 Digital frequency conversion technology

As can be seen from Figure 2, the conversion from the intermediate frequency sampling signal to the baseband signal is completed through digital frequency conversion. Digital frequency conversion technology is one of the core technologies of software radio, involving multi-rate digital signal processing (MRDSP) technology, which is an important technology in the field of digital signal processing that has been developed since the 1970s. The digital frequency converter mainly consists of three parts: digital mixer, digital controlled oscillator and low-pass filter. Digital frequency conversion uses orthogonal mixing, and the signal needs to be resampled, extracted or interpolated (the extraction filter here includes two steps, first anti-aliasing low-pass filtering, then sampling point extraction; interpolation filtering is first sampling point interpolation, then low-pass filtering to suppress image frequency). Because the intermediate frequency receiving signal has been converted into a baseband signal after orthogonal mixing, the signal now occupies only a small part within the intermediate frequency sampling band (half the intermediate frequency sampling rate). After low-pass decimation filtering, the data rate can be reduced (to the baseband sampling rate) while keeping the signal unaffected, which helps to reduce the pressure on the back-end digital signal processing; for the transmitting channel, interpolation filtering must be performed before orthogonal mixing to increase the signal data rate to at least twice the highest signal frequency required by the Nyquist sampling theorem, otherwise serious aliasing will occur.

In analog frequency conversion, the nonlinearity of the mixer and the frequency stability of the analog local oscillator, sideband, phase noise, temperature drift, conversion rate, etc. are the most concerned and difficult to completely solve problems. These problems do not exist in digital frequency conversion, and the frequency step and frequency interval also have ideal performance. Compared with analog frequency converters, digital frequency conversion also has the following advantages: ① The carrier frequency and digital filter coefficients are programmable; ② Digital mixing does not have nonlinear distortion, so intermodulation is small; ③ Digital filtering frequency response characteristics are good; ④ The system cost is low, etc.

There are a large number of dedicated programmable digital signal processors designed for digital frequency conversion on the market, such as Intersil's HSP50214/215, HSP50415, Graychip's GC1012, GC4014, and AD's AD9856, AD6620/22/24, etc. These chips have simpler instruction sets, faster speeds, and higher processing efficiency. The intermediate frequency digitization platform designed in this article uses two dedicated digital frequency conversion chips: HSP50415 and AD6620.

HSP50415 is a single-channel digital up-conversion chip from Intersil. This chip has strong modulation capability and is mainly composed of four parts: interpolation filter, complex modulator, timing and carrier digital control oscillator, and dual 12-bit 150M sampling rate D/A converter. The sampling rate conversion includes a 3-level interpolation filter with an interpolation range of 4 to 128K; supports orthogonal AM and PM modulation; provides pulse shaping filtering and constellation mapping, etc. The chip has a maximum output sampling rate of 100MSPS and a maximum input rate of 25MSPS. The front end has a 256-level deep FIFO; the 32-bit programmable digital control oscillator provides a maximum 50MHz carrier and 0.023Hz frequency accuracy.

The chip has 16 control registers and 4 trigger select registers, multiple configurable RAM blocks, and 2 external interfaces. uP NT ER FA CE is used for chip configuration and initialization, and DATAINTERFACE is used for I, Q quadrature data input. Figure 3 shows a reference interface circuit between the chip and TMS320C54x. When configuring the chip, since the internal control registers are mostly 32-bit word length, and the uP interface is only 8 bits wide, each control word needs to be loaded 4 times in succession to complete. During this period, the chip select line and the read and write lines must remain valid. When data is input, there are two methods, synchronous and asynchronous, depending on the generation of the driving clock DATACLK. The former directly connects the 2×SYMCLK (2 times the input code element clock) of HSP50415 to DATACLK as the data input driving clock. At this time, the code element input and output are strictly synchronized, and the FIFO at the front end of HSP50415 does not work. The DSP isolates the bus by controlling the input enable TXEN; the latter DATACLK is generated by the DSP through address decoding. When the DSP does not send data to the HSP50415, DATACLK is high and the bus is isolated. The DSP can determine whether to send data based on the interrupt status of the FIFO. This system adopts an interrupt-based asynchronous method.

The initialization of HSP50415 mainly includes setting carrier frequency, input symbol rate, FIFO interrupt type, shaping filter coefficient, channel gain, working mode and output mode, etc. The register values ​​for controlling carrier frequency and input symbol rate are calculated according to the following two formulas: Fsout is the output sampling rate, which is equal to the main clock of HSP50415, carrierFrequency is the carrier frequency, and symbolRate is the symbol rate, which is also the input sampling rate.

carrierNCOStep=(carrierFrequency/Fsout)×2^32

symbolNCOStep=(symbolRate/Fsout)×2^32

The key design of HSP50415 is the three-stage interpolation filter, whose design results directly affect the performance of the digital channel. The first-stage filter is a programmable FIR shaping filter, which mainly completes the first-stage interpolation filtering and signal shaping. This filter can be designed as a pulse shaping filter; the second-stage filter is a 19th-order half-band filter with fixed coefficients, which provides 2 times interpolation. The special structure of the half-band filter can reduce the amount of calculation by half compared with the FIR filter under the same number of taps; the third-stage filter is an interpolation filter, whose impulse response is similar to that of a cascaded integral comb filter, which can provide 2 to 8192 times interpolation and can achieve fractional times interpolation. The filter configuration is automatically completed by the chip.

AD6620 is a single-channel digital down-conversion chip from AD Company, with a maximum input rate of 67MSPS; the 32-bit complex NCO provides a frequency accuracy of 0.02Hz and phase and amplitude jitter correction; the sampling rate conversion includes a 3-stage decimation filter, namely a 2-stage cascaded CIC2 filter, a 5-stage cascaded CIC5 filter and a coefficient programmable FIR filter RCF; the data can be selected as a 16-bit parallel port output or a standard synchronous serial port output, and two independent control and configuration ports can dynamically configure the AD6620.

AD6620 has 14 control registers, one RCF coefficient RAM block and one RCF data RAM block. Generally, uP port (connected to DSP external data line) is used for chip configuration, and serial port is used to output down-converted data, so the interface logic is relatively simple. Figure 4 shows a reference interface scheme between AD6620 and TMS320C54x. The AD6620 serial port output adopts host mode, that is, AD6620 provides serial port clock and frame synchronization, and DSP receives data through serial port interrupt.

In this platform, the AD6620 front end uses the AD6640 for IF sampling. This chip is a 12-bit 65M sampling rate high-performance A/D converter, which is widely used in the field of IF broadband high-speed sampling. Combined with oversampling technology, it can further improve the sampling accuracy. The AD6620 and AD6640 use the same master clock, so that the maximum data throughput can be achieved between the two.

It is difficult to theoretically analyze how to configure the decimation rate of the three-stage decimation filter to obtain the best channel characteristics and the minimum amount of calculation. The decimation rate allocation scheme is limited when the number of cascades and the total decimation rate are certain. Therefore, computer-aided design can be used to exhaustively search for decimation rates at each level that meet the requirements, and the Parks-McClellan standard algorithm can be used to design the last-stage programmable FIR filter. This filter is mainly used for final-stage decimation and signal shaping, and has a great impact on channel performance. In addition, the AD6620 data document also provides a method for quickly determining the CIC2 and CIC5 decimation rates based on anti-aliasing indicators through simple calculation formulas and table lookups.

introduction

The purpose of software radio technology is to construct an open, standardized, and modular universal hardware platform, which uses software to complete various wireless communication functions, such as working frequency band, modulation and demodulation type, data format, encryption and anti-interference mode, communication protocol, etc., and to make broadband A/D and D/A converters as close to the antenna as possible. The ideal software radio structure is shown in Figure 1. Among them, N-/RT stands for punctual and real-time; the source/destination includes narrowband services and future broadband services.

Traditional shortwave radio stations are only suitable for transmitting analog voice and low-rate data due to the crowded frequency resources, severe frequency selective fading of time-varying ionospheric channels, multipath delay, various atmospheric noises and artificial radio noise. With the development of modern wireless communication theory and software and hardware technology and the in-depth exploration of ionospheric channel characteristics, shortwave radio stations have undergone the following changes: ① frequency hopping technology is used to improve anti-interference capabilities; ② adaptive communication technology is used to improve link building capabilities; ③ data communication (including graphic data and voice coded data, etc.) has become an important service mode; ④ digital encryption methods are used, etc.

Theoretically, the current ADC speed can meet the requirements of low-pass sampling of shortwave band signals, but there are the following problems when performing A/D conversion directly at the RF end. ① It seriously affects the selectivity and sensitivity of the receiver. Generally, there will be several strong narrowband interferences in the RF band. In order to prevent overload and reduce the quantization noise of the ADC, the ADC must have a large dynamic range. When the signal is very weak and close to the noise floor, the spurious-free dynamic range SFDR index of the ADC determines the total SNR of the receiver, and the implementation of the ADC is very difficult; ② The shortwave band bandwidth is relatively wide, and the performance of the broadband anti-aliasing filter and broadband amplifier before the ADC is not ideal at present; ③ It is very difficult for the digital signal processor to perform channel separation and demodulation of the narrowband signal in the RF band; ④ The signal-to-noise ratio deterioration caused by the ADC sampling aperture jitter is relatively serious. Therefore, the current digital transformation of traditional shortwave radio stations mostly retains the radio frequency and analog mixing links of the radio station, and is carried out at a lower and fixed second intermediate frequency.

The shortwave intermediate frequency digital platform designed in this paper is digitized at the second intermediate frequency 500kHz, thereby eliminating a series of analog demodulation links such as sideband filtering of traditional radio stations, and building a unified hardware platform to realize software modulation and demodulation of single sideband, amplitude modulation, and constant amplitude voice, and on this basis, load frequency hopping, adaptive, parallel and serial modem data transmission and other modulation and demodulation modules. The structural principle of the shortwave intermediate frequency digital platform is shown in Figure 2. Among them, N-RT is quasi-real time and real time; the source/destination includes narrowband services and future broadband services.

1 Digital frequency conversion technology

As can be seen from Figure 2, the conversion from the intermediate frequency sampling signal to the baseband signal is completed through digital frequency conversion. Digital frequency conversion technology is one of the core technologies of software radio, involving multi-rate digital signal processing (MRDSP) technology, which is an important technology in the field of digital signal processing that has been developed since the 1970s. The digital frequency converter mainly consists of three parts: digital mixer, digital controlled oscillator and low-pass filter. Digital frequency conversion uses orthogonal mixing, and the signal needs to be resampled, extracted or interpolated (the extraction filter here includes two steps, first anti-aliasing low-pass filtering, then sampling point extraction; interpolation filtering is first sampling point interpolation, then low-pass filtering to suppress image frequency). Because the intermediate frequency receiving signal has been converted into a baseband signal after orthogonal mixing, the signal now occupies only a small part within the intermediate frequency sampling band (half the intermediate frequency sampling rate). After low-pass decimation filtering, the data rate can be reduced (to the baseband sampling rate) while keeping the signal unaffected, which helps to reduce the pressure on the back-end digital signal processing; for the transmitting channel, interpolation filtering must be performed before orthogonal mixing to increase the signal data rate to at least twice the highest signal frequency required by the Nyquist sampling theorem, otherwise serious aliasing will occur.

In analog frequency conversion, the nonlinearity of the mixer and the frequency stability of the analog local oscillator, sideband, phase noise, temperature drift, conversion rate, etc. are the most concerned and difficult to completely solve problems. These problems do not exist in digital frequency conversion, and the frequency step and frequency interval also have ideal performance. Compared with analog frequency converters, digital frequency conversion also has the following advantages: ① The carrier frequency and digital filter coefficients are programmable; ② Digital mixing does not have nonlinear distortion, so intermodulation is small; ③ Digital filtering frequency response characteristics are good; ④ The system cost is low, etc.

There are a large number of dedicated programmable digital signal processors designed for digital frequency conversion on the market, such as Intersil's HSP50214/215, HSP50415, Graychip's GC1012, GC4014, and AD's AD9856, AD6620/22/24, etc. These chips have simpler instruction sets, faster speeds, and higher processing efficiency. The intermediate frequency digitization platform designed in this article uses two dedicated digital frequency conversion chips: HSP50415 and AD6620.

HSP50415 is a single-channel digital up-conversion chip from Intersil. This chip has strong modulation capability and is mainly composed of four parts: interpolation filter, complex modulator, timing and carrier digital control oscillator, and dual 12-bit 150M sampling rate D/A converter. The sampling rate conversion includes a 3-level interpolation filter with an interpolation range of 4 to 128K; supports orthogonal AM and PM modulation; provides pulse shaping filtering and constellation mapping, etc. The chip has a maximum output sampling rate of 100MSPS and a maximum input rate of 25MSPS. The front end has a 256-level deep FIFO; the 32-bit programmable digital control oscillator provides a maximum 50MHz carrier and 0.023Hz frequency accuracy.

The chip has 16 control registers and 4 trigger select registers, multiple configurable RAM blocks, and 2 external interfaces. uP NT ER FA CE is used for chip configuration and initialization, and DATAINTERFACE is used for I, Q quadrature data input. Figure 3 shows a reference interface circuit between the chip and TMS320C54x. When configuring the chip, since the internal control registers are mostly 32-bit word length, and the uP interface is only 8 bits wide, each control word needs to be loaded 4 times in succession to complete. During this period, the chip select line and the read and write lines must remain valid. When data is input, there are two methods, synchronous and asynchronous, depending on the generation of the driving clock DATACLK. The former directly connects the 2×SYMCLK (2 times the input code element clock) of HSP50415 to DATACLK as the data input driving clock. At this time, the code element input and output are strictly synchronized, and the FIFO at the front end of HSP50415 does not work. The DSP isolates the bus by controlling the input enable TXEN; the latter DATACLK is generated by the DSP through address decoding. When the DSP does not send data to the HSP50415, DATACLK is high and the bus is isolated. The DSP can determine whether to send data based on the interrupt status of the FIFO. This system adopts an interrupt-based asynchronous method.

The initialization of HSP50415 mainly includes setting carrier frequency, input symbol rate, FIFO interrupt type, shaping filter coefficient, channel gain, working mode and output mode, etc. The register values ​​for controlling carrier frequency and input symbol rate are calculated according to the following two formulas: Fsout is the output sampling rate, which is equal to the main clock of HSP50415, carrierFrequency is the carrier frequency, and symbolRate is the symbol rate, which is also the input sampling rate.

carrierNCOStep=(carrierFrequency/Fsout)×2^32

symbolNCOStep=(symbolRate/Fsout)×2^32

The key design of HSP50415 is the three-stage interpolation filter, whose design results directly affect the performance of the digital channel. The first-stage filter is a programmable FIR shaping filter, which mainly completes the first-stage interpolation filtering and signal shaping. This filter can be designed as a pulse shaping filter; the second-stage filter is a 19th-order half-band filter with fixed coefficients, which provides 2 times interpolation. The special structure of the half-band filter can reduce the amount of calculation by half compared with the FIR filter under the same number of taps; the third-stage filter is an interpolation filter, whose impulse response is similar to that of a cascaded integral comb filter, which can provide 2 to 8192 times interpolation and can achieve fractional times interpolation. The filter configuration is automatically completed by the chip.

AD6620 is a single-channel digital down-conversion chip from AD Company, with a maximum input rate of 67MSPS; the 32-bit complex NCO provides a frequency accuracy of 0.02Hz and phase and amplitude jitter correction; the sampling rate conversion includes a 3-stage decimation filter, namely a 2-stage cascaded CIC2 filter, a 5-stage cascaded CIC5 filter and a coefficient programmable FIR filter RCF; the data can be selected as a 16-bit parallel port output or a standard synchronous serial port output, and two independent control and configuration ports can dynamically configure the AD6620.

AD6620 has 14 control registers, one RCF coefficient RAM block and one RCF data RAM block. Generally, uP port (connected to DSP external data line) is used for chip configuration, and serial port is used to output down-converted data, so the interface logic is relatively simple. Figure 4 shows a reference interface scheme between AD6620 and TMS320C54x. The AD6620 serial port output adopts host mode, that is, AD6620 provides serial port clock and frame synchronization, and DSP receives data through serial port interrupt.

In this platform, the AD6620 front end uses the AD6640 for IF sampling. This chip is a 12-bit 65M sampling rate high-performance A/D converter, which is widely used in the field of IF broadband high-speed sampling. Combined with oversampling technology, it can further improve the sampling accuracy. The AD6620 and AD6640 use the same master clock, so that the maximum data throughput can be achieved between the two.

It is difficult to theoretically analyze how to configure the decimation rate of the three-stage decimation filter to obtain the best channel characteristics and the minimum amount of calculation. The decimation rate allocation scheme is limited when the number of cascades and the total decimation rate are certain. Therefore, computer-aided design can be used to exhaustively search for decimation rates at each level that meet the requirements, and the Parks-McClellan standard algorithm can be used to design the last-stage programmable FIR filter. This filter is mainly used for final-stage decimation and signal shaping, and has a great impact on channel performance. In addition, the AD6620 data document also provides a method for quickly determining the CIC2 and CIC5 decimation rates based on anti-aliasing indicators through simple calculation formulas and table lookups.