Precision clock de-jitter technology designed into Si5324

This article introduces the main features of Si5324, block diagram and typical application circuit diagram of I2C control mode and SPI control mode. Silabs' Si5324 is a precision clock multiplier/jitter attenuator for applications with steep motion performance less than 1ps. Si5324 uses two clock inputs with a frequency range from 2 kHz to 710 MHz, generates two output clocks with a frequency range from 2 kHz to 945 MHz, and can select frequencies up to 1.4GHz. The loop bandwidth is 4-525 Hz and meets the jitter indicators of ITU-T G.8251 and Telcordia GR253-CORE. It can be programmed by I2C or SPI and works with a single power supply of 1.8 ±5%, 2.5 ±10% or 3.3 V ±10%. It is mainly used in broadcast video such as 3G/HD/SD-SDI, packet optical transmission system (P-OTS), SONET OC-48/192/768, SDH/STM-16/64/256 line cards, GbE/10/40/100G Synchronous Ethernet, data conversion, wireless base stations and test and measurement, etc.

Si5324 Applications:
 Broadcast video –3G/HD/SD-SDI, Genlock  Packet Optical Transport Systems (P-OTS), MSPP  OTN OTU-1/2/3/4 Asynchronous Demapping (Gapped Clock)  SONET OC-48/192/768, SDH/STM-16/64/256 line cards  1/2/4/8/10G Fibre Channel line cards  GbE/10/40/100G Synchronous Ethernet (LAN/WAN)  Data converter clocking  Wireless base stations  Test and measurement Figure 1. Si5324 block diagram Figure 2. Si5324 typical application circuit diagram (I2C control mode) Figure 3. Si5324 typical application circuit diagram (SPI control mode)