Application of CPLD in the Design of Multifunctional Harmonic Analyzer

Application of CPLD in the Design of Multifunctional Harmonic Analyzer

1 Sampling method comparison When collecting data for three-phase voltage and current 6-channel analog quantities, there are generally two methods: ① Alternating sampling method of same-phase voltage and current: In one cycle of the measured signal , 256 points are sampled, of which 128 odd points are voltage sampling points; 128 even points are current sampling points. The time difference between sampling voltage and current is Δt=T/256 (T is the period of the measured signal). The phase error of the same-phase voltage and current caused by Δt is δui=360*f*n*Δt (degrees). In the formula, f is the frequency of the measured signal, and n is the harmonic number. From the above formula, it can be seen that the phase error increases with the increase of the time difference Δt and the harmonic number n, which is the fundamental reason for the existence and inconsistency of the phase difference. Another reason is that when the power grid frequency is distorted, since the sampling is timed sampling and cannot follow the frequency change, it will also cause measurement errors. ② Synchronous sampling method of same-phase voltage and current in the whole cycle: The same-phase voltage and current adopt the method of synchronous sampling and time-sharing transmission. In this way, there is no time difference problem, and there is no phase difference; for the problem of grid frequency distortion, the commonly used method is phase-locked loop technology. It extracts the grid fundamental signal by sampling the grid voltage signal, and then performs shaping processing to obtain a square wave signal with the same frequency as the fundamental signal, and then phase-locks it to obtain a square wave signal with an output frequency of f0=N*fi, which is used as a full-cycle synchronous sampling pulse signal. Therefore, the sampling interval also changes with the frequency of the measured signal, but this increases the hardware overhead. In this design, the full-cycle synchronous sampling method is adopted: the CPLD and the single-chip microcomputer cooperate to generate a full-cycle synchronous sampling pulse signal that meets the requirements. 2 Working principle and hardware composition 2.1 Working principle of the system First, let the measured signal be pre-processed by the anti-aliasing low-pass filter circuit, and one of the signals is accurately measured by the frequency measurement module, and the frequency parameters are transmitted to the single-chip microcomputer, which determines the frequency division coefficient through calculation, and then sends it back to the main controller of the CPLD, and the main controller generates a sampling pulse signal. During the sampling process, synchronous holding is used for the same-phase voltage and current signals, and time-sharing sampling is performed through a multi-way switch. Among them, the control signals Ca, Cb, Cc of the three-way sample holders and the address selection signals A1, A2, and A3 of the multi-way switch are generated by CPLD control. The selected signal is sent to the AD to start the conversion , and the conversion end signal is detected. When an AD conversion is completed, the result of the AD conversion is directly sent to the dual-port RAM for storage through the address and read-write control timing generated by the RAM address generator. Then, the next sampling is performed. After the sampling of the A phase signal is completed, the B phase and C phase signals are sampled sequentially. The MCS?51 microcontroller in this design is mainly responsible for the management of operations and human-machine interfaces, which will greatly improve the operating efficiency of the entire system, improve the accuracy of operations, and take into account the response speed of operations. 2.2 Selection of main hardware Since CPLD is a high-speed device, when the sampling frequency is very high, the multi-way switch and AD converter become the main factors restricting the sampling frequency. When the sampling frequency reaches the mega level, the storage speed of RAM becomes another restrictive factor. In this design, the harmonics to be analyzed are required to reach 50 times, and the measured signal is within the range of 45Hz to 55Hz, and the frequency automatically follows. According to Shannon's theorem, the sampling frequency should be greater than or equal to twice the frequency of the measured signal. It is required to sample 128 points per cycle, so the total sampling frequency is f=128*55*2=14.08kHz, so the sampling period is T=1/fs=71.02μs. The sample-and-hold device selects AD582, which is a feedback structure. When the accuracy requirement is not high (≤0.1%) and the speed requirement is high, CH=1000pF can be selected, and the capture time tAC≤6μs. The multi-way switch selects MAX382, which has a fast switching speed. Under the dual power supply and continuous power supply working mode, the typical switching time is about 100ns. Its main features are: low operating voltage, small channel resistance (≤100Ω), digital input latch, TTL/CMOS level compatibility, ESD electrostatic protection function, etc. The ADC converter uses MAX172, which is a 12-bit analog-to-digital conversion chip powered by 5V power supply. It is manufactured by CMOS process, has fast speed, conversion time of 10μs, has reference source, external clock, and frequency requirement of 1.25MHz. 2.3 Introduction to CPLD Devices In this design, EP1K100QC208-3 is selected, which is an FPGA chip under the ACEX1K series launched by ALTERA. The chip needs to be reconfigured when powered on. There are 100,000 available gates, 4,992 logic units, and 12 EABs embedded in the chip. The capacity of each EAB is 512Byte, which can easily construct RAM, ROM, FIFO or dual-port RAM and other functions. The 6KB dual-port RAM in this design is built on this basis. It has 208 pins and 147 available I/O pins. 3CPLD internal circuit implementation The software of this design is completed under MAX+plusII10.2. The top-level file is a *.gdf graphic file, and the lower level is described in AHDL hardware description language. 3.1 Frequency measurement module The main functions of the frequency measurement module are: ① measure the frequency of the power grid; ② determine the frequency division coefficient and generate synchronous pulses that follow the frequency changes. Frequency measurement principle: Since the measured frequency is around 50Hz, the pulse width measurement method is adopted, that is, the measured signal is first divided by 2 to make the positive and negative pulse widths of the signal equal, and then the positive pulse width is used to count the 50MHz standard pulse. When the positive pulse width rises, the counter starts counting the standard pulse; when the falling edge comes, the current count value Con is latched. The frequency f and the frequency division coefficient N are determined by the following relationship. The frequency division coefficient is: half of the ratio of the system clock source frequency to the divided pulse frequency (256*f) minus 1, that is, 3.2S/H timing control module Because the same-phase voltage and current synchronous sampling technology is adopted, the control timing of S/H is strictly required. The time for synchronously collecting a certain phase voltage and current once is ≤71.02μs. The same-phase voltage and current are required to be maintained at the same time and sampled in time. Since the capture time of ADC582 is about 6μs, the low level of the S/H timing pulse should be at least 10μs, during which the sample holder is in the tracking state; the high level is 60μs, during which the sample holder is in the holding state. The voltage signal is ADC-ed in the first 30μs.

































Convert and store; 30μs later, the current signal is converted to AD and stored. The simulation waveform is shown in Figure 2.

3.3 Address generation and ADC control module of the multi-way switch MAX382

During the high level period of one cycle of the AD582 control pulse, the voltage and current need to be collected once each, so the multi-way switch MAX382 needs to be strobed twice, and the AD chip MAX172 also needs to be started twice. The first MAX382 strobe starts at 1μs after the rising edge of the AD582 control pulse; the second starts at 31μs in the middle, with a delay of 1μs. This is because the output of the sample-and-hold device still has a period of fluctuation, and it remains stable after a certain period of time tST. In order to ensure accurate quantification, a delay of 1μs is issued after the hold instruction is issued. The AD start pulse starts at 2μs and 32μs of the AD582 control pulse, and is also delayed by 1μs. The control terminals of MAX172 are: CS, HEN, RD; the conversion end status line: BUSY. When CS=0, RD=0, BUSY=0, AD is converting; when BUSY=1, the conversion is finished; when HEN=1, read the high 4 bits of the conversion result, and when HEN=0, read the low 8 bits of the conversion result. This module needs to be simulated in combination with hardware. The control timing diagram of MAX172 is shown in Figure 3.

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3.4 Dual-port RAM address generator and read-write control module The ACEX1K100 device has an embedded EAB unit, which can form a dual-port RAM with a capacity of about ??KB. Since the MAX172 has ?-bit AD, and the data bus of the MCS-51 is only ??-bit, the data sampled ?? times is divided into ?? bytes and stored separately. Because the voltage and current are converted alternately in time sharing, there must be a certain mapping rule in the address generator to adjust its storage address so that the voltage and current are stored in blocks in the dual-port RAM. In addition, in the dual-port RAM, when the same address unit is read and written at the same time, there must be an arbitration mechanism to control it; when the read and write conflict occurs, we agree that the CPLD has priority in writing the dual-port RAM, and only when the write operation is completed, the MCS-51 microcontroller is allowed to read the unit. The simulation waveform of this module is shown in ??. 3.5 Communication module This module builds a serial transmission circuit port inside the CPLD to realize the communication function between the MCS-51 microcontroller and the CPLD device. (1) In normal working mode, important data such as frequency and division coefficient of synchronization pulse need to be communicated. (2) In system upgrade mode, the microcontroller sends control data to CPLD to realize upgrade. The communication mode is serial simplex communication, MCS-51 microcontroller sends data and CPLD receives data. The communication baud rate is agreed to be bps, and the communication frame structure is ?bit data??bit start bit (low level)??bit data bit, low bit in front??bit stop bit (high level). Between frames??bit idle bit (high level) to ensure correct communication. ? ? 4 Conclusion In the design of power harmonic analyzer, the application of CPLD greatly improves the sampling rate. Due to the use of frequency following technology, it can meet the needs of high-precision measurement. In addition, it also reduces the burden of MCS-51 microcontroller, improves the response speed of the system, and is more real-time. This design has another advantage, which is that the system is easy to upgrade. Just replace the ADC chip with MAX162 and modify the microcontroller program slightly. Of course, it can also realize online modification and remote control functions. References [1] Qiu Runhe, Ren Zihui, et al. Application of single chip microcomputer in power grid harmonic analyzer [J]. Journal of China University of Mining and Technology, 1994, 23(1). [2] Xu Huiming, Lu Jinfeng, et al. Several advanced technologies in the design of GXY-90 power frequency harmonic analyzer [J]. Chinese Journal of Instrumentation, 1994, 15(2). [3] Li Shaoming, Yang Weihan, et al. Design of high-speed data acquisition and harmonic analyzer [J]. Automation Instrumentation, 1999, (12). [4] Fu Huisheng, Yuan Xiaoping, Zhuang Qianqi. Complex programmable logic devices and application design [M]. China University of Mining and Technology Press, 2003.