Communication between EMIF and FPGA of TMS320C6455

Jacktang

Communication between EMIF and FPGA of TMS320C6455 [Copy link]

1. Brief Introduction of EMIF

The 64x EMIF is a parallel data transmission on-chip peripheral used for off-chip memory expansion and external data interface. The use process requires software to write a configuration program so that the hardware circuit of the on-chip peripheral can realize specific timing logic functions and form a seamless high-speed data transmission channel with external memory or peripheral devices. Therefore, the work of EMIF requires the cooperation of software and hardware, and it belongs to a hybrid matrix.

EMIF can be directly associated with the storage space through EDMA, and the entire data transmission can be parallel with the CPU operation, increasing the time efficiency of algorithm execution.

The figure shows the basic structure and interface signal diagram of EMIF. The basic structure of EMIF includes an EDMA controller linked to the 64x internal storage space, which is used to directly store external memory data into the 64x internal memory; the EMIF control register group is used to set the data transmission mode of EMIF. The setting of these registers determines the actual application function of EMIF and is one of the key links in EMIF design; there are many interface signals between EMIF and external memory to adapt to different memory types, such as SRAM, ROM, FLASH, and FPGA.

The following mainly explains the data transmission between EMIF and FPGA.

Although there are many interface signals, only a few are actually used, as shown in the red rectangles in the figure.

(1) Clock signal. In the figure, ECLKIN is the bus input clock, which is used to control the bus frequency of EMIF data transmission. ECLKOUT outputs the actual bus clock signal of EMIF, which is used to synchronize with external memory read/write. Regarding the clock setting, I have not yet fully understood it. The book says that the actual EMIF frequency can be set through the PLL register. Since I did it based on the project left by my senior, I did not find the code for setting the EMIF frequency. However, the EMIF clock period is set to 10ns in the constraint file of the FPGA. I don't quite understand the relationship between the two.

(2) Data/address signal. ED in the figure is the data line. EMIFA has a data length selection mode, which can be 8 bit, 16 bit, 32 bit, 64 bit. It can be set in the control register.

(3) Control signals. Control signals include memory read/write signals. When transmitting data with FPGA, only three signals, CE, AWE, and AOE, are used. CE is the chip select space enable signal, AWE is the DSP write data enable signal to the data bus, and AOE is the DSP read data enable signal from the data bus. When FPGA detects that CE and AOE are both low, it receives data sent by DSP; when FPGA detects that CE and AWE are both low, it sends data to DSP. Generally, when FPGA and DSP communicate data, FPGA receives and sends data through FIFO. The clock of FIFO is controlled by EMIF clock. The write enable or read enable of FIFO is controlled by CE, AWE and CE, AOE respectively.

(4) Chip select signal. EMIF has 4 groups of chip select signals. Each group selects a certain address space. Each group of chip select space is connected to different external memories. Generally, CE2 is selected for data transmission with FPGA.

2. Brief Introduction of EDMA

EDMA is an enhanced direct memory access method, which is mainly used for data transmission between the on-chip L2 cache and other peripherals. It has the ability of background batch data transmission independent of the CPU and can meet the requirements of high-speed data transmission in real-time image processing.

Since we use the TMS320C6x series DSP chip, we use EDMA3. EDMA3 has 64 channels, each channel has an event associated with it, each event is equivalent to a synchronization signal, and the event triggers the data transmission of the corresponding channel. In the absence of CPU participation, the EDMA controller can complete the data movement between the on-chip memory and the peripherals in the background.

In the data transmission between DSP and FPGA, the main function of EDMA is to move data blocks between storage spaces. It can transfer data from the storage address of EMIF chip select space to internal storage space or transfer data from internal space to the storage address of EMIF chip select space. The specific implementation will be explained in detail later.

2. Configuration in DSP

This section only records the used parts.

(1) Configuration of control registers

Refer to section 12.5 of the XILINX official document spru971e (TMS320C645x DSP External Memory Interface (EMIF)).

When SSEL is set to 1, it means that the CE corresponds to the external memory in synchronous mode. Only four data need to be set.

a: SBSIZE data bus length selection, can be set to 8, 16, 32, 64.

b: R_LTNCY read delay cycle. When CE and AOE are both low, it means that DSP starts to read the FPGA RAM, and after R_LTNCY ECLKOUT cycles, the first data appears on the data bus.

c: W_LTNCY write delay cycle. When CE and AWE are both low, it means that DSP starts writing data to the data bus. After W_LTNCY ECLKOUT cycles, the first data appears on the data bus.

d: R_ENABLE sets the SRE/SADS pin function.

(2) EDMA configuration

Refer to the official document: "C6455_CSL_APIREFERENCE"

First, define the data structure DAT_Setup and perform initialization configuration.

Then, call DAT_open, which I understand can configure EDMA.

Finally, call DAT_copy to move the data.

3. Configuration in FPGA

When the FPGA and DSP's EMIF are transmitting data, it is best to receive data through the fifo or send data through the fifo. This ensures that the FPGA and EMIF share the same clock during data transmission. Other modules of the FPGA can use different clocks.

(1) FPGA receives data sent by DSP

The fifo write enable fifo_wr_en is controlled by EMIF's CE and AWE. One data is written in one clock cycle.

(2) DSP receives data sent by FPGA

The read enable of fifo is controlled by CE and AOE of EMIF. One data is read out in one clock cycle.