Analysis and Implementation of Netlist in Integrated Circuit Testability Design

1. Introduction

As microelectronics manufacturing technology develops towards deep submicron, the integration of digital integrated circuits is getting higher and higher. Various failures may be introduced in semiconductor processes. In addition, material defects and process deviations may cause short circuits, open circuits and device junction punch-through in the circuit connection of the chip. Such physical failures will inevitably lead to circuit function or performance failures. In order to ensure the correctness of the design, the chip must be tested when it is manufactured and used. The most effective method at present is to use the design for testability technology (DFT, De-sign For Testability), that is, to ensure the testability of the circuit during design. The test of digital logic circuits includes functional testing and structural testing. Functional testing is to detect the common functions of the module in the working state of the system and to detect the interface connection between the module and the system. However, due to the complexity of the module, it is usually impossible to exhaust all functions and test them within a limited time. Structural circuit testing is a comprehensive test of the internal circuit structure to ensure the correctness of the functions implemented by the circuit. Structural circuit testing first needs to model the physical defects of the circuit, establish a fault model, and generate test stimuli. Then the test stimulus is introduced from the original input to the fault point, and the test response of the fault point is propagated to the original output of the circuit. Finally, the test response is compared with the fault-free response to determine whether the circuit has a fault. From 1986 to 1988, the Joint Test Action Group (JTAG), which mainly consists of European and North American members, took the lead in conducting research on boundary scan technology and proposed a series of JTAG boundary scan standard drafts. In 1990, TEEE and JTAC jointly launched the IEEE Std 1149.1 boundary scan standard. Its main idea is to add boundary scan units between the chip pins and the internal logic circuits of the chip, that is, on the boundary of the chip to achieve serial setting and reading of the chip pin status, thereby providing a standard test framework at the chip level, board level and system level. The chip scanning mechanism can achieve the following goals: test the connection between different chips on the circuit board; test the functions of the chip and the circuit board; use the boundary scan register to complete other test functions, such as feature analysis. In this project, boundary scan technology will be used to perform structural tests on AlteraDE2 and Cyclone II development boards to ensure the correctness of circuit functions. The basic test idea is to use a traversal method to detect the connectivity between different pins of multiple integrated devices on the development board. On the basis of ensuring connectivity, a test stimulus is introduced to determine whether the circuit has a corresponding response output. The most critical element is to extract the pin connections of the integrated device to be tested by parsing the netlist file of the development board. This paper analyzes the netlist structure and derives an effective method for parsing the netlist: first, for the cadence netlist file, read each line of data line by line, then perform semantic parsing on each line of data, extract relevant network information from it, and then select the component names to be tested, extract all the pins connected to these components, and save them in a new file. This file contains all the connection information of the device to be tested.

2. Netlist file format analysis

The format of the Cadence netlist consists of two parts, one is the definition of the component, and the other is the definition of the network. The details are as follows: 2.1 Component definition format The first part of the netlist is to define the components used. A typical component definition is as follows: Each component definition starts with the symbol "[" and ends with the symbol "]". The first line is the name of the component, that is, the Designator information; the second line is the component package, that is, the footprint information; the third line is the component annotation. 2.2 Network definition format The second half of the netlist is the network definition used in the circuit diagram. Each network definition corresponds to a point in the circuit that has an electrical connection relationship. A typical network definition is as follows: Each network definition starts with the symbol "(" and ends with the symbol ")". The first line under the "(" symbol is the name of the network. The following lines are the component identifiers and pin numbers of all components connected to the network point. For example, C2-2 means that the second pin of capacitor C2 is connected to the network. NetC2_2; X1-1 means that the first pin of crystal oscillator X1 is also connected to this network point. According to the analysis of the netlist format, it can be seen that each component has a fixed format: component name, component value, package type, number of pins, X coordinate, Y coordinate; devices are separated by []; the net follows the device; the content of each net is "component name-pin number" (Note: the number may be different); nets are separated by (). The development platform of this software is C++builder6.0, and the programming language used is C language. The basic idea is to start with the reading and parsing of the netlist file, first delete the component definition part from the netlist file, then extract the relevant network information according to the input name of the integrated device to be tested, and finally generate a pin connection file of the component to be tested with clear hierarchy and clear functions.

3. Analysis of the netlist parsing process

This paper introduces the method and process of parsing the circuit netlist file in the integrated circuit testability design project to extract the pin connections between the integrated devices to be tested. The requirements of the netlist extraction program are: based on the given netlist, first convert the netlist into a new netlist that is conducive to extracting network definition information, that is, delete all component definition information and power supply|regulator module and grounding module information from the original netlist file; then extract the corresponding pin connection information from the new netlist according to the name of the integrated component to be tested; finally, save the pin connection information in a file format that is easy to test. 3.1 Filtering of component information in the netlist file According to the analysis of the netlist format, it can be seen that it is more convenient to use a single-line reading method for the netlist, so each line of the file is read by calling the fgets() function. Since the information of each device is separated by "[]", "[" can be used as a sign of whether the component information has started, and "]" can be used as a sign of whether the component information has been read. For the old netlist, first declare a FILE pointer, use fopen("path to the old netlist", "r") to open the old netlist file, then use the fgets() function to read a line of information into a temporary character array str[], and use the strcmp() function to compare with "[" and "]" respectively to determine the beginning and end of a component information. In addition, the strcmp() function is used to compare with "(" to determine the end of the component definition and the beginning of the network information definition. According to the previous design ideas, we need to extract only the network information from the netlist file. Therefore, the feof() function is used to determine whether the end of the old netlist file has been read. If not, a line of information is read by calling the fgets() function. As long as it is not "(", it means that the line of information does not belong to the network definition part, and it is skipped with the continue statement; continue to read the next line until "(" is read, indicating that the network definition part has been read, and the line of information and all the information after it can be written into the new netlist file. When you open the new netlist file, you can see that the new netlist file has filtered out the component information part that is not related to the test in the old netlist file, and only retains the network definition part. The program flow of this part is shown in Figure 1. 3.2 After the new netlist file is successfully created, further analysis shows that the new netlist file contains some power modules, such as +1.2v, +1.8V, +2.5V, +3.3V, +5V, +12V, etc.; there are also ground modules GND, GNDC, etc. The information contained in these modules is still irrelevant to the test pins, so they still need to be filtered out. The method of filtering these power modules and ground modules is still to use the fgets() function to get each line of information in turn, and then call the strcmp() function to determine whether it is the corresponding power and ground module. If so, skip the file block of the module, starting from "(" and ending with ")". This part of the process is shown in Figure 2. 3.3 Analysis of the Generation Process of the Pin Connection File of the Device to be TestedAfter the above two steps, only net information remains in the netlist file. Enter the component name to be tested on the interface, then find the network node containing all the components to be tested in the new netlist file, and finally save the found network node in a new file in a certain format. Since what needs to be extracted in the new netlist file are the pin numbers of multiple components to be tested in the same network node, that is, the connection between these devices. Therefore, when using the fgets() function to read information line by line, first extract the component name from each line of information, and then compare the component name with the input component name to be tested. If they are consistent, write the line of information into the new file, otherwise read the next line of information. When the entire node information is read, the new file only saves the pin information that matches the component to be tested. The program flow of this part is shown in Figure 3.

4. Conclusion

This article mainly introduces the method and implementation process of parsing the netlist file of the Altera DE2 Cyclone II development board in the integrated circuit testability design project, extracting the pin connection of the device to be tested, and this method is also applicable to other netlist files. After testing, this software lays a very good foundation for realizing the structural test of the circuit by parsing the netlist file of the development board, which not only improves the quality assurance of the chip, but also improves the testability of the designed circuit, basically achieving the expected purpose.